Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8188148 |
1 |
|
|
T32 |
59364 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5876824 |
1 |
|
|
T32 |
48186 |
|
T1 |
10 |
|
T11 |
39940 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11720700 |
1 |
|
|
T32 |
89213 |
|
T33 |
341 |
|
T1 |
28 |
| auto[1] |
2344272 |
1 |
|
|
T32 |
18337 |
|
T1 |
1 |
|
T11 |
16040 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8196362 |
1 |
|
|
T32 |
60307 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5868610 |
1 |
|
|
T32 |
47243 |
|
T1 |
3 |
|
T11 |
39703 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1770404 |
1 |
|
|
T32 |
13350 |
|
T1 |
2 |
|
T11 |
11518 |
| auto[1] |
auto[0] |
auto[1] |
1176581 |
1 |
|
|
T32 |
8588 |
|
T1 |
1 |
|
T11 |
8005 |
| auto[1] |
auto[1] |
auto[0] |
1753934 |
1 |
|
|
T32 |
15556 |
|
T11 |
12145 |
|
T12 |
2402 |
| auto[1] |
auto[1] |
auto[1] |
1167691 |
1 |
|
|
T32 |
9749 |
|
T11 |
8035 |
|
T12 |
3126 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |