Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8180792 |
1 |
|
|
T32 |
57220 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5884180 |
1 |
|
|
T32 |
50330 |
|
T1 |
10 |
|
T11 |
41907 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11704604 |
1 |
|
|
T32 |
89766 |
|
T33 |
341 |
|
T1 |
24 |
| auto[1] |
2360368 |
1 |
|
|
T32 |
17784 |
|
T1 |
5 |
|
T11 |
16247 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8135887 |
1 |
|
|
T32 |
63073 |
|
T33 |
341 |
|
T1 |
24 |
| auto[1] |
5929085 |
1 |
|
|
T32 |
44477 |
|
T1 |
5 |
|
T11 |
40168 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1777831 |
1 |
|
|
T32 |
13233 |
|
T11 |
11810 |
|
T12 |
2476 |
| auto[1] |
auto[0] |
auto[1] |
1179590 |
1 |
|
|
T32 |
8755 |
|
T1 |
5 |
|
T11 |
8171 |
| auto[1] |
auto[1] |
auto[0] |
1790886 |
1 |
|
|
T32 |
13460 |
|
T11 |
12111 |
|
T12 |
2326 |
| auto[1] |
auto[1] |
auto[1] |
1180778 |
1 |
|
|
T32 |
9029 |
|
T11 |
8076 |
|
T12 |
3108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |