Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8207822 |
1 |
|
|
T32 |
60740 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5857150 |
1 |
|
|
T32 |
46810 |
|
T1 |
6 |
|
T11 |
42069 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11719829 |
1 |
|
|
T32 |
89330 |
|
T33 |
341 |
|
T1 |
27 |
| auto[1] |
2345143 |
1 |
|
|
T32 |
18220 |
|
T1 |
2 |
|
T11 |
15566 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8174159 |
1 |
|
|
T32 |
60917 |
|
T33 |
341 |
|
T1 |
27 |
| auto[1] |
5890813 |
1 |
|
|
T32 |
46633 |
|
T1 |
2 |
|
T11 |
39450 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1794989 |
1 |
|
|
T32 |
14154 |
|
T11 |
12147 |
|
T12 |
2157 |
| auto[1] |
auto[0] |
auto[1] |
1183415 |
1 |
|
|
T32 |
8767 |
|
T11 |
7585 |
|
T12 |
2875 |
| auto[1] |
auto[1] |
auto[0] |
1750681 |
1 |
|
|
T32 |
14259 |
|
T11 |
11737 |
|
T12 |
2220 |
| auto[1] |
auto[1] |
auto[1] |
1161728 |
1 |
|
|
T32 |
9453 |
|
T1 |
2 |
|
T11 |
7981 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |