Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8178389 |
1 |
|
|
T32 |
60534 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5886583 |
1 |
|
|
T32 |
47016 |
|
T1 |
4 |
|
T11 |
39902 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11732994 |
1 |
|
|
T32 |
88476 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
2331978 |
1 |
|
|
T32 |
19074 |
|
T1 |
6 |
|
T11 |
16584 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8201604 |
1 |
|
|
T32 |
58043 |
|
T33 |
341 |
|
T1 |
20 |
| auto[1] |
5863368 |
1 |
|
|
T32 |
49507 |
|
T1 |
9 |
|
T11 |
41189 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1770710 |
1 |
|
|
T32 |
15449 |
|
T1 |
1 |
|
T11 |
12395 |
| auto[1] |
auto[0] |
auto[1] |
1163996 |
1 |
|
|
T32 |
9585 |
|
T1 |
6 |
|
T11 |
8530 |
| auto[1] |
auto[1] |
auto[0] |
1760680 |
1 |
|
|
T32 |
14984 |
|
T1 |
2 |
|
T11 |
12210 |
| auto[1] |
auto[1] |
auto[1] |
1167982 |
1 |
|
|
T32 |
9489 |
|
T11 |
8054 |
|
T12 |
3081 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |