Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2558614 |
1 |
|
|
T32 |
18942 |
|
T1 |
4 |
|
T11 |
17005 |
| auto[1] |
auto[0] |
auto[1] |
374834 |
1 |
|
|
T32 |
2672 |
|
T11 |
2442 |
|
T12 |
752 |
| auto[1] |
auto[1] |
auto[0] |
2552681 |
1 |
|
|
T32 |
21680 |
|
T11 |
17947 |
|
T12 |
5322 |
| auto[1] |
auto[1] |
auto[1] |
372455 |
1 |
|
|
T32 |
3226 |
|
T11 |
2690 |
|
T12 |
919 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |