Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8153617 |
1 |
|
|
T32 |
60047 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5911355 |
1 |
|
|
T32 |
47503 |
|
T1 |
6 |
|
T11 |
41120 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11713899 |
1 |
|
|
T32 |
89055 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
2351073 |
1 |
|
|
T32 |
18495 |
|
T1 |
7 |
|
T11 |
15797 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8146998 |
1 |
|
|
T32 |
59893 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5917974 |
1 |
|
|
T32 |
47657 |
|
T1 |
7 |
|
T11 |
40462 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1772381 |
1 |
|
|
T32 |
14338 |
|
T11 |
11866 |
|
T12 |
2186 |
| auto[1] |
auto[0] |
auto[1] |
1169784 |
1 |
|
|
T32 |
8924 |
|
T1 |
7 |
|
T11 |
7621 |
| auto[1] |
auto[1] |
auto[0] |
1794520 |
1 |
|
|
T32 |
14824 |
|
T11 |
12799 |
|
T12 |
1988 |
| auto[1] |
auto[1] |
auto[1] |
1181289 |
1 |
|
|
T32 |
9571 |
|
T11 |
8176 |
|
T12 |
2740 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |