Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8168024 |
1 |
|
|
T32 |
61293 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5896948 |
1 |
|
|
T32 |
46257 |
|
T1 |
6 |
|
T11 |
40083 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11733448 |
1 |
|
|
T32 |
89024 |
|
T33 |
341 |
|
T1 |
28 |
| auto[1] |
2331524 |
1 |
|
|
T32 |
18526 |
|
T1 |
1 |
|
T11 |
16290 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8210750 |
1 |
|
|
T32 |
60315 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5854222 |
1 |
|
|
T32 |
47235 |
|
T1 |
7 |
|
T11 |
41798 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1755969 |
1 |
|
|
T32 |
14750 |
|
T1 |
4 |
|
T11 |
13192 |
| auto[1] |
auto[0] |
auto[1] |
1165398 |
1 |
|
|
T32 |
9497 |
|
T1 |
1 |
|
T11 |
8374 |
| auto[1] |
auto[1] |
auto[0] |
1766729 |
1 |
|
|
T32 |
13959 |
|
T1 |
2 |
|
T11 |
12316 |
| auto[1] |
auto[1] |
auto[1] |
1166126 |
1 |
|
|
T32 |
9029 |
|
T11 |
7916 |
|
T12 |
3204 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |