Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8201646 |
1 |
|
|
T32 |
60123 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5863326 |
1 |
|
|
T32 |
47427 |
|
T1 |
6 |
|
T11 |
41480 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11709154 |
1 |
|
|
T32 |
90425 |
|
T33 |
341 |
|
T1 |
27 |
| auto[1] |
2355818 |
1 |
|
|
T32 |
17125 |
|
T1 |
2 |
|
T11 |
16083 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8160032 |
1 |
|
|
T32 |
63478 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5904940 |
1 |
|
|
T32 |
44072 |
|
T1 |
6 |
|
T11 |
41088 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1786303 |
1 |
|
|
T32 |
13826 |
|
T1 |
2 |
|
T11 |
12809 |
| auto[1] |
auto[0] |
auto[1] |
1184333 |
1 |
|
|
T32 |
8803 |
|
T1 |
2 |
|
T11 |
8014 |
| auto[1] |
auto[1] |
auto[0] |
1762819 |
1 |
|
|
T32 |
13121 |
|
T1 |
2 |
|
T11 |
12196 |
| auto[1] |
auto[1] |
auto[1] |
1171485 |
1 |
|
|
T32 |
8322 |
|
T11 |
8069 |
|
T12 |
2916 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |