Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8179308 |
1 |
|
|
T32 |
61044 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5885664 |
1 |
|
|
T32 |
46506 |
|
T1 |
10 |
|
T11 |
41894 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11722868 |
1 |
|
|
T32 |
88992 |
|
T33 |
341 |
|
T1 |
27 |
| auto[1] |
2342104 |
1 |
|
|
T32 |
18558 |
|
T1 |
2 |
|
T11 |
15697 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8169282 |
1 |
|
|
T32 |
59872 |
|
T33 |
341 |
|
T1 |
27 |
| auto[1] |
5895690 |
1 |
|
|
T32 |
47678 |
|
T1 |
2 |
|
T11 |
39643 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1784194 |
1 |
|
|
T32 |
15599 |
|
T11 |
11761 |
|
T12 |
2306 |
| auto[1] |
auto[0] |
auto[1] |
1179351 |
1 |
|
|
T32 |
9364 |
|
T11 |
7567 |
|
T12 |
3323 |
| auto[1] |
auto[1] |
auto[0] |
1769392 |
1 |
|
|
T32 |
13521 |
|
T11 |
12185 |
|
T12 |
2100 |
| auto[1] |
auto[1] |
auto[1] |
1162753 |
1 |
|
|
T32 |
9194 |
|
T1 |
2 |
|
T11 |
8130 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |