Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8169889 |
1 |
|
|
T32 |
61420 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5895083 |
1 |
|
|
T32 |
46130 |
|
T1 |
6 |
|
T11 |
41490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11710816 |
1 |
|
|
T32 |
89264 |
|
T33 |
341 |
|
T1 |
28 |
| auto[1] |
2354156 |
1 |
|
|
T32 |
18286 |
|
T1 |
1 |
|
T11 |
16454 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8152894 |
1 |
|
|
T32 |
59619 |
|
T33 |
341 |
|
T1 |
24 |
| auto[1] |
5912078 |
1 |
|
|
T32 |
47931 |
|
T1 |
5 |
|
T11 |
42124 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1782408 |
1 |
|
|
T32 |
15749 |
|
T1 |
2 |
|
T11 |
12588 |
| auto[1] |
auto[0] |
auto[1] |
1179890 |
1 |
|
|
T32 |
9417 |
|
T1 |
1 |
|
T11 |
8323 |
| auto[1] |
auto[1] |
auto[0] |
1775514 |
1 |
|
|
T32 |
13896 |
|
T1 |
2 |
|
T11 |
13082 |
| auto[1] |
auto[1] |
auto[1] |
1174266 |
1 |
|
|
T32 |
8869 |
|
T11 |
8131 |
|
T12 |
2904 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |