Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8133569 |
1 |
|
|
T32 |
62853 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5931403 |
1 |
|
|
T32 |
44697 |
|
T1 |
6 |
|
T11 |
39430 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11733322 |
1 |
|
|
T32 |
90198 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
2331650 |
1 |
|
|
T32 |
17352 |
|
T11 |
15822 |
|
T12 |
6532 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8187073 |
1 |
|
|
T32 |
63614 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5877899 |
1 |
|
|
T32 |
43936 |
|
T11 |
40483 |
|
T12 |
11090 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1772089 |
1 |
|
|
T32 |
14320 |
|
T11 |
12798 |
|
T12 |
2033 |
| auto[1] |
auto[0] |
auto[1] |
1163634 |
1 |
|
|
T32 |
9085 |
|
T11 |
8156 |
|
T12 |
3126 |
| auto[1] |
auto[1] |
auto[0] |
1774160 |
1 |
|
|
T32 |
12264 |
|
T11 |
11863 |
|
T12 |
2525 |
| auto[1] |
auto[1] |
auto[1] |
1168016 |
1 |
|
|
T32 |
8267 |
|
T11 |
7666 |
|
T12 |
3406 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |