Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8201134 |
1 |
|
|
T32 |
62441 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5863838 |
1 |
|
|
T32 |
45109 |
|
T1 |
6 |
|
T11 |
41708 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11713985 |
1 |
|
|
T32 |
88972 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
2350987 |
1 |
|
|
T32 |
18578 |
|
T1 |
4 |
|
T11 |
16725 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8164687 |
1 |
|
|
T32 |
60370 |
|
T33 |
341 |
|
T1 |
20 |
| auto[1] |
5900285 |
1 |
|
|
T32 |
47180 |
|
T1 |
9 |
|
T11 |
41918 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1794934 |
1 |
|
|
T32 |
15031 |
|
T1 |
5 |
|
T11 |
12187 |
| auto[1] |
auto[0] |
auto[1] |
1182767 |
1 |
|
|
T32 |
9683 |
|
T1 |
2 |
|
T11 |
7983 |
| auto[1] |
auto[1] |
auto[0] |
1754364 |
1 |
|
|
T32 |
13571 |
|
T11 |
13006 |
|
T12 |
2458 |
| auto[1] |
auto[1] |
auto[1] |
1168220 |
1 |
|
|
T32 |
8895 |
|
T1 |
2 |
|
T11 |
8742 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |