Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8171040 |
1 |
|
|
T32 |
62039 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5893932 |
1 |
|
|
T32 |
45511 |
|
T1 |
4 |
|
T11 |
40463 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11718111 |
1 |
|
|
T32 |
89101 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
2346861 |
1 |
|
|
T32 |
18449 |
|
T1 |
4 |
|
T11 |
17137 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8181568 |
1 |
|
|
T32 |
59993 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5883404 |
1 |
|
|
T32 |
47557 |
|
T1 |
4 |
|
T11 |
42773 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1761862 |
1 |
|
|
T32 |
14830 |
|
T11 |
13185 |
|
T12 |
2294 |
| auto[1] |
auto[0] |
auto[1] |
1173210 |
1 |
|
|
T32 |
9092 |
|
T1 |
2 |
|
T11 |
8740 |
| auto[1] |
auto[1] |
auto[0] |
1774681 |
1 |
|
|
T32 |
14278 |
|
T11 |
12451 |
|
T12 |
2073 |
| auto[1] |
auto[1] |
auto[1] |
1173651 |
1 |
|
|
T32 |
9357 |
|
T1 |
2 |
|
T11 |
8397 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |