Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8189136 |
1 |
|
|
T32 |
59407 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5875836 |
1 |
|
|
T32 |
48143 |
|
T1 |
10 |
|
T11 |
40645 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11726642 |
1 |
|
|
T32 |
89965 |
|
T33 |
341 |
|
T1 |
27 |
| auto[1] |
2338330 |
1 |
|
|
T32 |
17585 |
|
T1 |
2 |
|
T11 |
16370 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8189210 |
1 |
|
|
T32 |
61144 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5875762 |
1 |
|
|
T32 |
46406 |
|
T1 |
4 |
|
T11 |
41403 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1760598 |
1 |
|
|
T32 |
13682 |
|
T1 |
2 |
|
T11 |
12467 |
| auto[1] |
auto[0] |
auto[1] |
1165936 |
1 |
|
|
T32 |
8750 |
|
T11 |
8398 |
|
T12 |
3029 |
| auto[1] |
auto[1] |
auto[0] |
1776834 |
1 |
|
|
T32 |
15139 |
|
T11 |
12566 |
|
T12 |
2172 |
| auto[1] |
auto[1] |
auto[1] |
1172394 |
1 |
|
|
T32 |
8835 |
|
T1 |
2 |
|
T11 |
7972 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |