Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218738 |
1 |
|
|
T32 |
60343 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5846234 |
1 |
|
|
T32 |
47207 |
|
T11 |
40754 |
|
T12 |
9925 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13318792 |
1 |
|
|
T32 |
101629 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
746180 |
1 |
|
|
T32 |
5921 |
|
T11 |
4924 |
|
T12 |
1406 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8201319 |
1 |
|
|
T32 |
61830 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5863653 |
1 |
|
|
T32 |
45720 |
|
T1 |
7 |
|
T11 |
38696 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2580975 |
1 |
|
|
T32 |
20695 |
|
T1 |
7 |
|
T11 |
17506 |
| auto[1] |
auto[0] |
auto[1] |
377624 |
1 |
|
|
T32 |
3126 |
|
T11 |
2578 |
|
T12 |
779 |
| auto[1] |
auto[1] |
auto[0] |
2536498 |
1 |
|
|
T32 |
19104 |
|
T11 |
16266 |
|
T12 |
3796 |
| auto[1] |
auto[1] |
auto[1] |
368556 |
1 |
|
|
T32 |
2795 |
|
T11 |
2346 |
|
T12 |
627 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |