Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8187198 |
1 |
|
|
T32 |
60610 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5877774 |
1 |
|
|
T32 |
46940 |
|
T11 |
41397 |
|
T12 |
10853 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11729681 |
1 |
|
|
T32 |
89764 |
|
T33 |
341 |
|
T1 |
24 |
| auto[1] |
2335291 |
1 |
|
|
T32 |
17786 |
|
T1 |
5 |
|
T11 |
16162 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8195965 |
1 |
|
|
T32 |
61989 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5869007 |
1 |
|
|
T32 |
45561 |
|
T1 |
7 |
|
T11 |
40619 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1765637 |
1 |
|
|
T32 |
13782 |
|
T1 |
2 |
|
T11 |
12325 |
| auto[1] |
auto[0] |
auto[1] |
1166541 |
1 |
|
|
T32 |
8745 |
|
T1 |
5 |
|
T11 |
8040 |
| auto[1] |
auto[1] |
auto[0] |
1768079 |
1 |
|
|
T32 |
13993 |
|
T11 |
12132 |
|
T12 |
2387 |
| auto[1] |
auto[1] |
auto[1] |
1168750 |
1 |
|
|
T32 |
9041 |
|
T11 |
8122 |
|
T12 |
3076 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |