Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8188599 |
1 |
|
|
T32 |
59013 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5876373 |
1 |
|
|
T32 |
48537 |
|
T1 |
10 |
|
T11 |
40125 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11726625 |
1 |
|
|
T32 |
89118 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
2338347 |
1 |
|
|
T32 |
18432 |
|
T11 |
15236 |
|
T12 |
6450 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8199147 |
1 |
|
|
T32 |
59818 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5865825 |
1 |
|
|
T32 |
47732 |
|
T1 |
4 |
|
T11 |
38821 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1765694 |
1 |
|
|
T32 |
14109 |
|
T1 |
2 |
|
T11 |
11717 |
| auto[1] |
auto[0] |
auto[1] |
1167718 |
1 |
|
|
T32 |
8901 |
|
T11 |
7795 |
|
T12 |
2781 |
| auto[1] |
auto[1] |
auto[0] |
1761784 |
1 |
|
|
T32 |
15191 |
|
T1 |
2 |
|
T11 |
11868 |
| auto[1] |
auto[1] |
auto[1] |
1170629 |
1 |
|
|
T32 |
9531 |
|
T11 |
7441 |
|
T12 |
3669 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |