Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8210519 |
1 |
|
|
T32 |
58794 |
|
T33 |
341 |
|
T1 |
29 |
auto[1] |
5854453 |
1 |
|
|
T32 |
48756 |
|
T11 |
39004 |
|
T12 |
10940 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13324114 |
1 |
|
|
T32 |
101452 |
|
T33 |
341 |
|
T1 |
29 |
auto[1] |
740858 |
1 |
|
|
T32 |
6098 |
|
T11 |
5019 |
|
T12 |
1420 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8229175 |
1 |
|
|
T32 |
60664 |
|
T33 |
341 |
|
T1 |
29 |
auto[1] |
5835797 |
1 |
|
|
T32 |
46886 |
|
T11 |
40091 |
|
T12 |
10038 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2560811 |
1 |
|
|
T32 |
19603 |
|
T11 |
18611 |
|
T12 |
4315 |
auto[1] |
auto[0] |
auto[1] |
372701 |
1 |
|
|
T32 |
2914 |
|
T11 |
2701 |
|
T12 |
707 |
auto[1] |
auto[1] |
auto[0] |
2534128 |
1 |
|
|
T32 |
21185 |
|
T11 |
16461 |
|
T12 |
4303 |
auto[1] |
auto[1] |
auto[1] |
368157 |
1 |
|
|
T32 |
3184 |
|
T11 |
2318 |
|
T12 |
713 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |