Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8161758 |
1 |
|
|
T32 |
61093 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5903214 |
1 |
|
|
T32 |
46457 |
|
T1 |
10 |
|
T11 |
40942 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13311229 |
1 |
|
|
T32 |
101506 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
753743 |
1 |
|
|
T32 |
6044 |
|
T11 |
5271 |
|
T12 |
1524 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8150489 |
1 |
|
|
T32 |
60404 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5914483 |
1 |
|
|
T32 |
47146 |
|
T1 |
3 |
|
T11 |
41470 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2582416 |
1 |
|
|
T32 |
20552 |
|
T11 |
18487 |
|
T12 |
4058 |
| auto[1] |
auto[0] |
auto[1] |
377425 |
1 |
|
|
T32 |
2966 |
|
T11 |
2683 |
|
T12 |
667 |
| auto[1] |
auto[1] |
auto[0] |
2578324 |
1 |
|
|
T32 |
20550 |
|
T1 |
3 |
|
T11 |
17712 |
| auto[1] |
auto[1] |
auto[1] |
376318 |
1 |
|
|
T32 |
3078 |
|
T11 |
2588 |
|
T12 |
857 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |