Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8178916 |
1 |
|
|
T32 |
61142 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5886056 |
1 |
|
|
T32 |
46408 |
|
T11 |
40964 |
|
T12 |
10555 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13319473 |
1 |
|
|
T32 |
101565 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
745499 |
1 |
|
|
T32 |
5985 |
|
T11 |
5140 |
|
T12 |
1483 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8198850 |
1 |
|
|
T32 |
61509 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5866122 |
1 |
|
|
T32 |
46041 |
|
T1 |
3 |
|
T11 |
39850 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2554554 |
1 |
|
|
T32 |
20211 |
|
T1 |
3 |
|
T11 |
16824 |
| auto[1] |
auto[0] |
auto[1] |
371739 |
1 |
|
|
T32 |
3011 |
|
T11 |
2458 |
|
T12 |
764 |
| auto[1] |
auto[1] |
auto[0] |
2566069 |
1 |
|
|
T32 |
19845 |
|
T11 |
17886 |
|
T12 |
4548 |
| auto[1] |
auto[1] |
auto[1] |
373760 |
1 |
|
|
T32 |
2974 |
|
T11 |
2682 |
|
T12 |
719 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |