Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8198600 |
1 |
|
|
T32 |
59798 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5866372 |
1 |
|
|
T32 |
47752 |
|
T1 |
10 |
|
T11 |
41607 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13314222 |
1 |
|
|
T32 |
101556 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
750750 |
1 |
|
|
T32 |
5994 |
|
T11 |
5170 |
|
T12 |
1535 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8176153 |
1 |
|
|
T32 |
60479 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5888819 |
1 |
|
|
T32 |
47071 |
|
T1 |
7 |
|
T11 |
40222 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2578387 |
1 |
|
|
T32 |
19734 |
|
T1 |
4 |
|
T11 |
17348 |
| auto[1] |
auto[0] |
auto[1] |
377638 |
1 |
|
|
T32 |
2908 |
|
T11 |
2557 |
|
T12 |
774 |
| auto[1] |
auto[1] |
auto[0] |
2559682 |
1 |
|
|
T32 |
21343 |
|
T1 |
3 |
|
T11 |
17704 |
| auto[1] |
auto[1] |
auto[1] |
373112 |
1 |
|
|
T32 |
3086 |
|
T11 |
2613 |
|
T12 |
761 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |