Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8170767 |
1 |
|
|
T32 |
59389 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5894205 |
1 |
|
|
T32 |
48161 |
|
T1 |
6 |
|
T11 |
39572 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13316437 |
1 |
|
|
T32 |
101704 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
748535 |
1 |
|
|
T32 |
5846 |
|
T11 |
5233 |
|
T12 |
1586 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8194488 |
1 |
|
|
T32 |
61692 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5870484 |
1 |
|
|
T32 |
45858 |
|
T1 |
3 |
|
T11 |
40332 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2560519 |
1 |
|
|
T32 |
20048 |
|
T11 |
18334 |
|
T12 |
4398 |
| auto[1] |
auto[0] |
auto[1] |
372825 |
1 |
|
|
T32 |
2959 |
|
T11 |
2742 |
|
T12 |
674 |
| auto[1] |
auto[1] |
auto[0] |
2561430 |
1 |
|
|
T32 |
19964 |
|
T1 |
3 |
|
T11 |
16765 |
| auto[1] |
auto[1] |
auto[1] |
375710 |
1 |
|
|
T32 |
2887 |
|
T11 |
2491 |
|
T12 |
912 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |