Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T759 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1845639160 Jul 19 04:29:52 PM PDT 24 Jul 19 04:30:01 PM PDT 24 67046995 ps
T760 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3157694355 Jul 19 04:29:56 PM PDT 24 Jul 19 04:30:07 PM PDT 24 55231689 ps
T761 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1971280571 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:58 PM PDT 24 33996484 ps
T50 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3579181264 Jul 19 04:29:49 PM PDT 24 Jul 19 04:29:57 PM PDT 24 41482180 ps
T105 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2290987940 Jul 19 04:29:57 PM PDT 24 Jul 19 04:30:08 PM PDT 24 40029002 ps
T762 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.686288844 Jul 19 04:29:48 PM PDT 24 Jul 19 04:29:55 PM PDT 24 63529386 ps
T763 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3039615534 Jul 19 04:30:10 PM PDT 24 Jul 19 04:30:20 PM PDT 24 47004743 ps
T764 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2368789590 Jul 19 04:30:00 PM PDT 24 Jul 19 04:30:12 PM PDT 24 481218331 ps
T765 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1303902879 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:57 PM PDT 24 39204830 ps
T766 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4286199596 Jul 19 04:29:57 PM PDT 24 Jul 19 04:30:09 PM PDT 24 596708322 ps
T767 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2190285644 Jul 19 04:29:59 PM PDT 24 Jul 19 04:30:11 PM PDT 24 47354588 ps
T768 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3726016847 Jul 19 04:30:09 PM PDT 24 Jul 19 04:30:19 PM PDT 24 15583880 ps
T127 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3639646459 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:58 PM PDT 24 431618480 ps
T769 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2691677994 Jul 19 04:30:02 PM PDT 24 Jul 19 04:30:14 PM PDT 24 31444272 ps
T770 /workspace/coverage/cover_reg_top/42.gpio_intr_test.4277279472 Jul 19 04:30:08 PM PDT 24 Jul 19 04:30:19 PM PDT 24 42067068 ps
T771 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1927580849 Jul 19 04:30:13 PM PDT 24 Jul 19 04:30:22 PM PDT 24 20364974 ps
T772 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3559707152 Jul 19 04:30:11 PM PDT 24 Jul 19 04:30:21 PM PDT 24 17365005 ps
T773 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1492891825 Jul 19 04:30:01 PM PDT 24 Jul 19 04:30:13 PM PDT 24 33860821 ps
T774 /workspace/coverage/cover_reg_top/11.gpio_intr_test.535375674 Jul 19 04:29:53 PM PDT 24 Jul 19 04:30:03 PM PDT 24 34231967 ps
T775 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1717876419 Jul 19 04:29:44 PM PDT 24 Jul 19 04:29:49 PM PDT 24 22009575 ps
T776 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.884902612 Jul 19 04:29:52 PM PDT 24 Jul 19 04:30:02 PM PDT 24 36896308 ps
T777 /workspace/coverage/cover_reg_top/14.gpio_intr_test.257683137 Jul 19 04:29:58 PM PDT 24 Jul 19 04:30:10 PM PDT 24 86005081 ps
T778 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2033191127 Jul 19 04:29:54 PM PDT 24 Jul 19 04:30:04 PM PDT 24 11031511 ps
T779 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1656595929 Jul 19 04:30:05 PM PDT 24 Jul 19 04:30:16 PM PDT 24 59002975 ps
T780 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1035617737 Jul 19 04:29:59 PM PDT 24 Jul 19 04:30:10 PM PDT 24 18943841 ps
T781 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.4147276454 Jul 19 04:29:49 PM PDT 24 Jul 19 04:29:58 PM PDT 24 99004953 ps
T782 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2707524478 Jul 19 04:29:52 PM PDT 24 Jul 19 04:30:02 PM PDT 24 21440125 ps
T783 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.589014664 Jul 19 04:29:58 PM PDT 24 Jul 19 04:30:10 PM PDT 24 223521609 ps
T784 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3950174077 Jul 19 04:30:09 PM PDT 24 Jul 19 04:30:20 PM PDT 24 43257196 ps
T785 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.331990757 Jul 19 04:30:06 PM PDT 24 Jul 19 04:30:18 PM PDT 24 244569997 ps
T786 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.391472980 Jul 19 04:29:52 PM PDT 24 Jul 19 04:30:01 PM PDT 24 48755697 ps
T787 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2897762148 Jul 19 04:30:10 PM PDT 24 Jul 19 04:30:20 PM PDT 24 16018098 ps
T788 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1794937915 Jul 19 04:30:00 PM PDT 24 Jul 19 04:30:14 PM PDT 24 322257196 ps
T789 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1216265437 Jul 19 04:29:42 PM PDT 24 Jul 19 04:29:46 PM PDT 24 56488138 ps
T790 /workspace/coverage/cover_reg_top/12.gpio_intr_test.2070750897 Jul 19 04:30:00 PM PDT 24 Jul 19 04:30:11 PM PDT 24 15958384 ps
T49 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.590468824 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:58 PM PDT 24 430675454 ps
T791 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3328660430 Jul 19 04:30:12 PM PDT 24 Jul 19 04:30:21 PM PDT 24 25415178 ps
T792 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3971319584 Jul 19 04:30:01 PM PDT 24 Jul 19 04:30:13 PM PDT 24 54446414 ps
T793 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3295948601 Jul 19 04:29:48 PM PDT 24 Jul 19 04:29:56 PM PDT 24 43450195 ps
T794 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2058831590 Jul 19 04:29:59 PM PDT 24 Jul 19 04:30:12 PM PDT 24 309187100 ps
T795 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1037359072 Jul 19 04:29:45 PM PDT 24 Jul 19 04:29:51 PM PDT 24 13721281 ps
T106 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1325182728 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:57 PM PDT 24 75158961 ps
T796 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1615571438 Jul 19 04:30:00 PM PDT 24 Jul 19 04:30:12 PM PDT 24 59642130 ps
T797 /workspace/coverage/cover_reg_top/34.gpio_intr_test.688795927 Jul 19 04:30:11 PM PDT 24 Jul 19 04:30:21 PM PDT 24 17031534 ps
T107 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.4054483554 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:58 PM PDT 24 65193093 ps
T798 /workspace/coverage/cover_reg_top/0.gpio_intr_test.710803743 Jul 19 04:29:44 PM PDT 24 Jul 19 04:29:48 PM PDT 24 15657900 ps
T799 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2132407448 Jul 19 04:29:47 PM PDT 24 Jul 19 04:29:55 PM PDT 24 193479194 ps
T800 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.145423339 Jul 19 04:29:54 PM PDT 24 Jul 19 04:30:05 PM PDT 24 510926565 ps
T801 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.55833619 Jul 19 04:29:53 PM PDT 24 Jul 19 04:30:04 PM PDT 24 490014266 ps
T802 /workspace/coverage/cover_reg_top/21.gpio_intr_test.269099161 Jul 19 04:30:02 PM PDT 24 Jul 19 04:30:14 PM PDT 24 15892248 ps
T803 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.883914223 Jul 19 04:30:03 PM PDT 24 Jul 19 04:30:15 PM PDT 24 213978396 ps
T804 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2102833493 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:58 PM PDT 24 403311211 ps
T805 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3381957841 Jul 19 04:30:00 PM PDT 24 Jul 19 04:30:12 PM PDT 24 222105962 ps
T806 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1520860409 Jul 19 04:29:49 PM PDT 24 Jul 19 04:29:59 PM PDT 24 59162721 ps
T807 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3486794086 Jul 19 04:29:46 PM PDT 24 Jul 19 04:29:53 PM PDT 24 78466715 ps
T108 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2467254523 Jul 19 04:29:47 PM PDT 24 Jul 19 04:29:55 PM PDT 24 65455243 ps
T808 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.348893114 Jul 19 04:29:56 PM PDT 24 Jul 19 04:30:07 PM PDT 24 209728399 ps
T809 /workspace/coverage/cover_reg_top/49.gpio_intr_test.314106874 Jul 19 04:30:12 PM PDT 24 Jul 19 04:30:21 PM PDT 24 17156110 ps
T810 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.374184892 Jul 19 04:29:57 PM PDT 24 Jul 19 04:30:08 PM PDT 24 41641640 ps
T811 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2326039625 Jul 19 04:29:51 PM PDT 24 Jul 19 04:29:59 PM PDT 24 14925308 ps
T812 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1886646921 Jul 19 04:29:47 PM PDT 24 Jul 19 04:29:55 PM PDT 24 171039305 ps
T813 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3093410284 Jul 19 04:29:58 PM PDT 24 Jul 19 04:30:09 PM PDT 24 12295903 ps
T814 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4266786626 Jul 19 04:29:52 PM PDT 24 Jul 19 04:30:01 PM PDT 24 273447907 ps
T815 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1424448147 Jul 19 04:30:04 PM PDT 24 Jul 19 04:30:16 PM PDT 24 98325859 ps
T816 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3135633477 Jul 19 04:30:05 PM PDT 24 Jul 19 04:30:17 PM PDT 24 65258562 ps
T817 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2453427091 Jul 19 04:30:08 PM PDT 24 Jul 19 04:30:19 PM PDT 24 98968253 ps
T818 /workspace/coverage/cover_reg_top/22.gpio_intr_test.677456758 Jul 19 04:30:05 PM PDT 24 Jul 19 04:30:16 PM PDT 24 12694592 ps
T819 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2398508738 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:59 PM PDT 24 687795160 ps
T820 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.769142297 Jul 19 04:30:06 PM PDT 24 Jul 19 04:30:17 PM PDT 24 92249979 ps
T821 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4067504616 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:58 PM PDT 24 141824555 ps
T822 /workspace/coverage/cover_reg_top/4.gpio_intr_test.8416426 Jul 19 04:30:00 PM PDT 24 Jul 19 04:30:11 PM PDT 24 12040785 ps
T823 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2000844269 Jul 19 04:30:04 PM PDT 24 Jul 19 04:30:16 PM PDT 24 21302149 ps
T824 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3427496810 Jul 19 04:29:53 PM PDT 24 Jul 19 04:30:04 PM PDT 24 35777716 ps
T825 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.859819127 Jul 19 04:30:01 PM PDT 24 Jul 19 04:30:13 PM PDT 24 57791227 ps
T826 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.270771608 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:58 PM PDT 24 16551372 ps
T827 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2635067711 Jul 19 04:29:52 PM PDT 24 Jul 19 04:30:01 PM PDT 24 27408519 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.882911151 Jul 19 04:29:58 PM PDT 24 Jul 19 04:30:09 PM PDT 24 36998051 ps
T829 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2700195606 Jul 19 04:29:51 PM PDT 24 Jul 19 04:29:59 PM PDT 24 356320805 ps
T830 /workspace/coverage/cover_reg_top/35.gpio_intr_test.386011293 Jul 19 04:30:08 PM PDT 24 Jul 19 04:30:19 PM PDT 24 83985056 ps
T831 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3273896418 Jul 19 04:30:11 PM PDT 24 Jul 19 04:30:21 PM PDT 24 58537833 ps
T832 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3932565617 Jul 19 04:30:03 PM PDT 24 Jul 19 04:30:14 PM PDT 24 27081289 ps
T833 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3584974418 Jul 19 04:29:46 PM PDT 24 Jul 19 04:29:52 PM PDT 24 339615198 ps
T834 /workspace/coverage/cover_reg_top/20.gpio_intr_test.4114747531 Jul 19 04:30:06 PM PDT 24 Jul 19 04:30:17 PM PDT 24 51720239 ps
T835 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3264258651 Jul 19 04:30:03 PM PDT 24 Jul 19 04:30:15 PM PDT 24 11418289 ps
T836 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4200562296 Jul 19 04:30:05 PM PDT 24 Jul 19 04:30:17 PM PDT 24 22634189 ps
T837 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1846727637 Jul 19 04:29:50 PM PDT 24 Jul 19 04:29:58 PM PDT 24 33729150 ps
T838 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2030680268 Jul 19 04:29:56 PM PDT 24 Jul 19 04:30:07 PM PDT 24 42813206 ps
T839 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1029405239 Jul 19 04:29:56 PM PDT 24 Jul 19 04:30:08 PM PDT 24 24819712 ps
T109 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2341061997 Jul 19 04:29:44 PM PDT 24 Jul 19 04:29:49 PM PDT 24 106121367 ps
T840 /workspace/coverage/cover_reg_top/47.gpio_intr_test.260324318 Jul 19 04:30:09 PM PDT 24 Jul 19 04:30:20 PM PDT 24 11929016 ps
T841 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1874596878 Jul 19 04:31:02 PM PDT 24 Jul 19 04:31:20 PM PDT 24 232511782 ps
T842 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2662801929 Jul 19 04:31:14 PM PDT 24 Jul 19 04:31:31 PM PDT 24 78115403 ps
T843 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.521655820 Jul 19 04:31:21 PM PDT 24 Jul 19 04:31:39 PM PDT 24 225395980 ps
T844 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2094986902 Jul 19 04:30:54 PM PDT 24 Jul 19 04:31:11 PM PDT 24 74086269 ps
T845 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2470798913 Jul 19 04:30:54 PM PDT 24 Jul 19 04:31:10 PM PDT 24 90208274 ps
T846 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3377251961 Jul 19 04:31:13 PM PDT 24 Jul 19 04:31:30 PM PDT 24 233705566 ps
T847 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2198210612 Jul 19 04:30:59 PM PDT 24 Jul 19 04:31:17 PM PDT 24 184225873 ps
T848 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3805843369 Jul 19 04:31:07 PM PDT 24 Jul 19 04:31:25 PM PDT 24 55515357 ps
T849 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2579274187 Jul 19 04:31:06 PM PDT 24 Jul 19 04:31:24 PM PDT 24 83782433 ps
T850 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.347485369 Jul 19 04:30:54 PM PDT 24 Jul 19 04:31:10 PM PDT 24 53993239 ps
T851 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2114479663 Jul 19 04:30:52 PM PDT 24 Jul 19 04:31:06 PM PDT 24 228017290 ps
T852 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2758751478 Jul 19 04:30:53 PM PDT 24 Jul 19 04:31:08 PM PDT 24 130672402 ps
T853 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1699755992 Jul 19 04:30:50 PM PDT 24 Jul 19 04:30:58 PM PDT 24 91685544 ps
T854 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3555109915 Jul 19 04:31:43 PM PDT 24 Jul 19 04:31:51 PM PDT 24 34232023 ps
T855 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750866327 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:11 PM PDT 24 71375945 ps
T856 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3608357000 Jul 19 04:31:24 PM PDT 24 Jul 19 04:31:41 PM PDT 24 55873563 ps
T857 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2562055930 Jul 19 04:30:58 PM PDT 24 Jul 19 04:31:16 PM PDT 24 67393622 ps
T858 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2157875917 Jul 19 04:31:06 PM PDT 24 Jul 19 04:31:24 PM PDT 24 122818102 ps
T859 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.112698615 Jul 19 04:31:06 PM PDT 24 Jul 19 04:31:24 PM PDT 24 39475086 ps
T860 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.106045121 Jul 19 04:30:54 PM PDT 24 Jul 19 04:31:11 PM PDT 24 43662878 ps
T861 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.974212623 Jul 19 04:30:49 PM PDT 24 Jul 19 04:30:55 PM PDT 24 191400477 ps
T862 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3206218262 Jul 19 04:31:03 PM PDT 24 Jul 19 04:31:21 PM PDT 24 143898479 ps
T863 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2129266487 Jul 19 04:31:24 PM PDT 24 Jul 19 04:31:42 PM PDT 24 47428728 ps
T864 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1306186795 Jul 19 04:31:07 PM PDT 24 Jul 19 04:31:25 PM PDT 24 80818832 ps
T865 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2583090313 Jul 19 04:30:54 PM PDT 24 Jul 19 04:31:09 PM PDT 24 112554180 ps
T866 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.100153379 Jul 19 04:30:52 PM PDT 24 Jul 19 04:31:06 PM PDT 24 163213348 ps
T867 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1110335077 Jul 19 04:31:04 PM PDT 24 Jul 19 04:31:22 PM PDT 24 76587304 ps
T868 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4241155842 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:12 PM PDT 24 270754918 ps
T869 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3987019320 Jul 19 04:31:06 PM PDT 24 Jul 19 04:31:24 PM PDT 24 77783266 ps
T870 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4104332483 Jul 19 04:30:58 PM PDT 24 Jul 19 04:31:16 PM PDT 24 532319603 ps
T871 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.562948334 Jul 19 04:30:52 PM PDT 24 Jul 19 04:31:07 PM PDT 24 247279836 ps
T872 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2326550772 Jul 19 04:31:12 PM PDT 24 Jul 19 04:31:29 PM PDT 24 49624624 ps
T873 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1646231204 Jul 19 04:30:54 PM PDT 24 Jul 19 04:31:09 PM PDT 24 90151028 ps
T874 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2788463223 Jul 19 04:31:00 PM PDT 24 Jul 19 04:31:18 PM PDT 24 49108366 ps
T875 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1111069122 Jul 19 04:31:29 PM PDT 24 Jul 19 04:31:46 PM PDT 24 162942279 ps
T876 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2795134733 Jul 19 04:31:01 PM PDT 24 Jul 19 04:31:19 PM PDT 24 392326630 ps
T877 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.878240538 Jul 19 04:31:16 PM PDT 24 Jul 19 04:31:33 PM PDT 24 71968304 ps
T878 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2479540339 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:13 PM PDT 24 191159792 ps
T879 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.201704968 Jul 19 04:31:24 PM PDT 24 Jul 19 04:31:42 PM PDT 24 132608730 ps
T880 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.897642685 Jul 19 04:31:00 PM PDT 24 Jul 19 04:31:18 PM PDT 24 157945210 ps
T881 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3257088765 Jul 19 04:30:56 PM PDT 24 Jul 19 04:31:14 PM PDT 24 50617640 ps
T882 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1446314662 Jul 19 04:31:01 PM PDT 24 Jul 19 04:31:18 PM PDT 24 95147989 ps
T883 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3147611954 Jul 19 04:30:49 PM PDT 24 Jul 19 04:30:54 PM PDT 24 102921074 ps
T884 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1422484696 Jul 19 04:30:53 PM PDT 24 Jul 19 04:31:08 PM PDT 24 211890742 ps
T885 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1502995719 Jul 19 04:31:04 PM PDT 24 Jul 19 04:31:22 PM PDT 24 140138454 ps
T886 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.729579308 Jul 19 04:31:04 PM PDT 24 Jul 19 04:31:21 PM PDT 24 155083890 ps
T887 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3665584030 Jul 19 04:31:00 PM PDT 24 Jul 19 04:31:17 PM PDT 24 381231254 ps
T888 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.359984116 Jul 19 04:30:52 PM PDT 24 Jul 19 04:31:06 PM PDT 24 166818804 ps
T889 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3054516445 Jul 19 04:30:59 PM PDT 24 Jul 19 04:31:17 PM PDT 24 85533120 ps
T890 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3158697490 Jul 19 04:30:54 PM PDT 24 Jul 19 04:31:11 PM PDT 24 105754320 ps
T891 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2438967335 Jul 19 04:30:51 PM PDT 24 Jul 19 04:31:03 PM PDT 24 254436331 ps
T892 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.624920735 Jul 19 04:31:23 PM PDT 24 Jul 19 04:31:41 PM PDT 24 48845697 ps
T893 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3228790742 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:11 PM PDT 24 39484645 ps
T894 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2724545692 Jul 19 04:30:58 PM PDT 24 Jul 19 04:31:16 PM PDT 24 46963987 ps
T895 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.90506403 Jul 19 04:30:59 PM PDT 24 Jul 19 04:31:17 PM PDT 24 204617503 ps
T896 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2829119610 Jul 19 04:30:58 PM PDT 24 Jul 19 04:31:16 PM PDT 24 650265014 ps
T897 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4077155211 Jul 19 04:30:53 PM PDT 24 Jul 19 04:31:09 PM PDT 24 757761619 ps
T898 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3539810087 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:13 PM PDT 24 83691180 ps
T899 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.936318085 Jul 19 04:31:04 PM PDT 24 Jul 19 04:31:22 PM PDT 24 43361926 ps
T900 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2534661506 Jul 19 04:31:07 PM PDT 24 Jul 19 04:31:25 PM PDT 24 240852125 ps
T901 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2654678971 Jul 19 04:31:01 PM PDT 24 Jul 19 04:31:19 PM PDT 24 152445595 ps
T902 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.178759590 Jul 19 04:30:54 PM PDT 24 Jul 19 04:31:11 PM PDT 24 269858463 ps
T903 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2905191928 Jul 19 04:30:50 PM PDT 24 Jul 19 04:30:58 PM PDT 24 133420692 ps
T904 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3955985210 Jul 19 04:30:59 PM PDT 24 Jul 19 04:31:17 PM PDT 24 175289138 ps
T905 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.962621711 Jul 19 04:31:17 PM PDT 24 Jul 19 04:31:33 PM PDT 24 71109953 ps
T906 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.42654434 Jul 19 04:30:51 PM PDT 24 Jul 19 04:31:04 PM PDT 24 93609722 ps
T907 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1733442201 Jul 19 04:30:52 PM PDT 24 Jul 19 04:31:06 PM PDT 24 196685657 ps
T908 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2340876983 Jul 19 04:30:49 PM PDT 24 Jul 19 04:30:55 PM PDT 24 84170184 ps
T909 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043859747 Jul 19 04:30:56 PM PDT 24 Jul 19 04:31:13 PM PDT 24 78980446 ps
T910 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4205732886 Jul 19 04:30:50 PM PDT 24 Jul 19 04:31:02 PM PDT 24 75513578 ps
T911 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3371580011 Jul 19 04:31:19 PM PDT 24 Jul 19 04:31:37 PM PDT 24 136382425 ps
T912 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1952401143 Jul 19 04:31:09 PM PDT 24 Jul 19 04:31:27 PM PDT 24 96624458 ps
T913 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1774844782 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:12 PM PDT 24 83565555 ps
T914 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3874609306 Jul 19 04:31:18 PM PDT 24 Jul 19 04:31:36 PM PDT 24 113251645 ps
T915 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.876617265 Jul 19 04:31:02 PM PDT 24 Jul 19 04:31:20 PM PDT 24 36721723 ps
T916 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1630275503 Jul 19 04:31:00 PM PDT 24 Jul 19 04:31:18 PM PDT 24 61733172 ps
T917 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4258551162 Jul 19 04:30:50 PM PDT 24 Jul 19 04:30:58 PM PDT 24 36528169 ps
T918 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.341021669 Jul 19 04:31:04 PM PDT 24 Jul 19 04:31:22 PM PDT 24 93871729 ps
T919 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2419139387 Jul 19 04:30:50 PM PDT 24 Jul 19 04:31:02 PM PDT 24 142666658 ps
T920 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3350536827 Jul 19 04:30:58 PM PDT 24 Jul 19 04:31:16 PM PDT 24 44840396 ps
T921 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3733518405 Jul 19 04:30:59 PM PDT 24 Jul 19 04:31:17 PM PDT 24 245396597 ps
T922 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.984841415 Jul 19 04:31:00 PM PDT 24 Jul 19 04:31:18 PM PDT 24 1921604878 ps
T923 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1242099208 Jul 19 04:30:53 PM PDT 24 Jul 19 04:31:09 PM PDT 24 82852528 ps
T924 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2033716088 Jul 19 04:30:54 PM PDT 24 Jul 19 04:31:11 PM PDT 24 89331955 ps
T925 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4067481465 Jul 19 04:31:24 PM PDT 24 Jul 19 04:31:42 PM PDT 24 35171508 ps
T926 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.739011720 Jul 19 04:31:10 PM PDT 24 Jul 19 04:31:28 PM PDT 24 25978488 ps
T927 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.605254905 Jul 19 04:31:05 PM PDT 24 Jul 19 04:31:23 PM PDT 24 119003125 ps
T928 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.920669033 Jul 19 04:31:02 PM PDT 24 Jul 19 04:31:20 PM PDT 24 228023950 ps
T929 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3699205085 Jul 19 04:31:06 PM PDT 24 Jul 19 04:31:24 PM PDT 24 62604850 ps
T930 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3831108290 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:12 PM PDT 24 332637844 ps
T931 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1887857206 Jul 19 04:30:56 PM PDT 24 Jul 19 04:31:13 PM PDT 24 153846378 ps
T932 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4161606451 Jul 19 04:31:01 PM PDT 24 Jul 19 04:31:20 PM PDT 24 121060873 ps
T933 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3178868058 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:12 PM PDT 24 47419248 ps
T934 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2396851690 Jul 19 04:31:29 PM PDT 24 Jul 19 04:31:46 PM PDT 24 76809979 ps
T935 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3422866246 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:12 PM PDT 24 167610231 ps
T936 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.969688486 Jul 19 04:30:55 PM PDT 24 Jul 19 04:31:13 PM PDT 24 169021133 ps
T937 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.822425403 Jul 19 04:31:00 PM PDT 24 Jul 19 04:31:18 PM PDT 24 76034574 ps
T938 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2064257200 Jul 19 04:31:17 PM PDT 24 Jul 19 04:31:34 PM PDT 24 204531682 ps
T939 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.804371695 Jul 19 04:30:51 PM PDT 24 Jul 19 04:31:04 PM PDT 24 77074516 ps
T940 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2004537450 Jul 19 04:31:08 PM PDT 24 Jul 19 04:31:26 PM PDT 24 69183061 ps

Test location /workspace/coverage/default/3.gpio_full_random.1181075155
Short name T14
Test name
Test status
Simulation time 290629440 ps
CPU time 0.99 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:30 PM PDT 24
Peak memory 196872 kb
Host smart-4ca0d629-fe4d-496c-86b7-19b16f7a04e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181075155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1181075155
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.879608017
Short name T69
Test name
Test status
Simulation time 78657118 ps
CPU time 2.92 seconds
Started Jul 19 04:44:33 PM PDT 24
Finished Jul 19 04:44:43 PM PDT 24
Peak memory 198248 kb
Host smart-8f795d40-488d-4564-8168-dabb617ab6db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879608017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.879608017
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1559540028
Short name T130
Test name
Test status
Simulation time 2242632007 ps
CPU time 31.19 seconds
Started Jul 19 04:44:31 PM PDT 24
Finished Jul 19 04:45:09 PM PDT 24
Peak memory 198324 kb
Host smart-2f2e9043-dd48-412c-815d-f0cb8f7e8d9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559540028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1559540028
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.389215751
Short name T20
Test name
Test status
Simulation time 147746694289 ps
CPU time 574.61 seconds
Started Jul 19 04:44:42 PM PDT 24
Finished Jul 19 04:54:21 PM PDT 24
Peak memory 198508 kb
Host smart-3243d71a-604f-4a13-936d-659c38397673
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=389215751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.389215751
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2486590173
Short name T16
Test name
Test status
Simulation time 16444516 ps
CPU time 0.6 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:12 PM PDT 24
Peak memory 194392 kb
Host smart-16a90bd3-c246-4962-b14c-6152ef51cdac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486590173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2486590173
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4121494472
Short name T85
Test name
Test status
Simulation time 15681980 ps
CPU time 0.63 seconds
Started Jul 19 04:29:58 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 194992 kb
Host smart-e56691c6-0407-4ff3-8148-210443d6318c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121494472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.4121494472
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1003560119
Short name T46
Test name
Test status
Simulation time 443848130 ps
CPU time 1.34 seconds
Started Jul 19 04:29:52 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 198172 kb
Host smart-921316c0-e67b-4d2e-ab46-391302f0ba57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003560119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1003560119
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/12.gpio_stress_all.368090084
Short name T6
Test name
Test status
Simulation time 44157794030 ps
CPU time 132.28 seconds
Started Jul 19 04:43:38 PM PDT 24
Finished Jul 19 04:45:56 PM PDT 24
Peak memory 198320 kb
Host smart-65e87a5e-802c-4cc1-be7f-a634b0fecf61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368090084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.368090084
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1209309747
Short name T52
Test name
Test status
Simulation time 130908690 ps
CPU time 0.78 seconds
Started Jul 19 04:43:24 PM PDT 24
Finished Jul 19 04:43:27 PM PDT 24
Peak memory 214152 kb
Host smart-75009147-57c8-4d88-98cc-a41aaa3b7eb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209309747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1209309747
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3041933697
Short name T44
Test name
Test status
Simulation time 117351321 ps
CPU time 1.41 seconds
Started Jul 19 04:30:04 PM PDT 24
Finished Jul 19 04:30:17 PM PDT 24
Peak memory 197916 kb
Host smart-4b71b572-e227-45a8-8d65-558b757d48f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041933697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3041933697
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/10.gpio_smoke.2594650523
Short name T15
Test name
Test status
Simulation time 89665816 ps
CPU time 0.75 seconds
Started Jul 19 04:43:39 PM PDT 24
Finished Jul 19 04:43:46 PM PDT 24
Peak memory 195992 kb
Host smart-4b3ff62d-a6c5-4458-95ed-5db833e2ed69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594650523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2594650523
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3925281886
Short name T111
Test name
Test status
Simulation time 45850004 ps
CPU time 0.73 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:29:43 PM PDT 24
Peak memory 196932 kb
Host smart-7999a413-6969-4012-95aa-062214ccb3a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925281886 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3925281886
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1846727637
Short name T837
Test name
Test status
Simulation time 33729150 ps
CPU time 0.8 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 196116 kb
Host smart-fe189530-ce87-408c-a81d-7c1eeaaef3a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846727637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1846727637
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2467254523
Short name T108
Test name
Test status
Simulation time 65455243 ps
CPU time 1.34 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:29:55 PM PDT 24
Peak memory 196888 kb
Host smart-ac5268a9-d784-4cb2-b73e-cd04a3f2e99c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467254523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2467254523
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2341061997
Short name T109
Test name
Test status
Simulation time 106121367 ps
CPU time 0.67 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:29:49 PM PDT 24
Peak memory 195728 kb
Host smart-21d065fb-1347-46d9-8480-4e8e3997d0f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341061997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2341061997
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3481237296
Short name T750
Test name
Test status
Simulation time 28951906 ps
CPU time 1.34 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 198256 kb
Host smart-42a2be8a-20b5-4f23-be90-9af2819493fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481237296 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3481237296
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2677488971
Short name T82
Test name
Test status
Simulation time 44083509 ps
CPU time 0.6 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:29:49 PM PDT 24
Peak memory 194980 kb
Host smart-4d2fe56d-c01e-4db3-a4d3-b31b7bcb30f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677488971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2677488971
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.710803743
Short name T798
Test name
Test status
Simulation time 15657900 ps
CPU time 0.6 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:29:48 PM PDT 24
Peak memory 194544 kb
Host smart-2d7177c2-43ad-48b1-9c4c-1c93370877c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710803743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.710803743
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.136955461
Short name T714
Test name
Test status
Simulation time 210142124 ps
CPU time 3.14 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:29:52 PM PDT 24
Peak memory 198196 kb
Host smart-01eca1df-cd35-43bc-adf2-bd015004eb11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136955461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.136955461
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3584974418
Short name T833
Test name
Test status
Simulation time 339615198 ps
CPU time 0.79 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:29:52 PM PDT 24
Peak memory 197948 kb
Host smart-0f178262-7c44-4f8d-8c44-242fec3dfe5c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584974418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3584974418
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3220215261
Short name T103
Test name
Test status
Simulation time 30422970 ps
CPU time 0.76 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:29:49 PM PDT 24
Peak memory 196432 kb
Host smart-6b0b3d55-3109-49cf-a5b3-2f6c9dc5c69a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220215261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3220215261
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2132407448
Short name T799
Test name
Test status
Simulation time 193479194 ps
CPU time 2.15 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:29:55 PM PDT 24
Peak memory 198144 kb
Host smart-0e06219a-b788-4809-9ca2-a9f7d87b2f0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132407448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2132407448
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1325182728
Short name T106
Test name
Test status
Simulation time 75158961 ps
CPU time 0.63 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 194840 kb
Host smart-dd274496-02d3-427f-aac8-8360f1efc212
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325182728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1325182728
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1971280571
Short name T761
Test name
Test status
Simulation time 33996484 ps
CPU time 0.71 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 197688 kb
Host smart-59577730-6f4c-4477-b4bd-8a732675dd05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971280571 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1971280571
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3086309672
Short name T732
Test name
Test status
Simulation time 15594801 ps
CPU time 0.6 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:29:49 PM PDT 24
Peak memory 194844 kb
Host smart-9c4563cd-ee5a-409b-afaf-0e92a25afe4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086309672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3086309672
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1717876419
Short name T775
Test name
Test status
Simulation time 22009575 ps
CPU time 0.57 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:29:49 PM PDT 24
Peak memory 193928 kb
Host smart-d3eb902e-0364-473b-ab7a-7bc1a3c218cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717876419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1717876419
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1037359072
Short name T795
Test name
Test status
Simulation time 13721281 ps
CPU time 0.66 seconds
Started Jul 19 04:29:45 PM PDT 24
Finished Jul 19 04:29:51 PM PDT 24
Peak memory 194872 kb
Host smart-6cef85ac-3a89-47a9-b294-4ec665f09cbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037359072 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1037359072
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1216265437
Short name T789
Test name
Test status
Simulation time 56488138 ps
CPU time 1.38 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:29:46 PM PDT 24
Peak memory 198220 kb
Host smart-d56f9578-1916-463b-b7ab-4425239e3980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216265437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1216265437
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.912452994
Short name T39
Test name
Test status
Simulation time 518278478 ps
CPU time 1.44 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:29:55 PM PDT 24
Peak memory 198372 kb
Host smart-cb92de42-dc49-45b3-a811-2056ca1fbc1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912452994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.912452994
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3427496810
Short name T824
Test name
Test status
Simulation time 35777716 ps
CPU time 1.55 seconds
Started Jul 19 04:29:53 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 198240 kb
Host smart-1b6147f8-8a98-4d24-8bc6-d1857db5be88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427496810 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3427496810
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3276398509
Short name T736
Test name
Test status
Simulation time 77501577 ps
CPU time 0.6 seconds
Started Jul 19 04:29:51 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 194816 kb
Host smart-89e4d057-a0b4-419a-8378-5d1338d66f7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276398509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3276398509
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1160423861
Short name T738
Test name
Test status
Simulation time 15105402 ps
CPU time 0.59 seconds
Started Jul 19 04:30:04 PM PDT 24
Finished Jul 19 04:30:15 PM PDT 24
Peak memory 194480 kb
Host smart-0e94ab36-70c0-4862-a871-fc7779a52662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160423861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1160423861
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3765877738
Short name T110
Test name
Test status
Simulation time 110638720 ps
CPU time 0.91 seconds
Started Jul 19 04:29:53 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 196240 kb
Host smart-90f30fab-6885-48df-b8a2-1a271e545b51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765877738 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3765877738
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1424448147
Short name T815
Test name
Test status
Simulation time 98325859 ps
CPU time 1.41 seconds
Started Jul 19 04:30:04 PM PDT 24
Finished Jul 19 04:30:16 PM PDT 24
Peak memory 198060 kb
Host smart-3ad5d288-1841-4d9a-8ec1-05ca414662e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424448147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1424448147
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2967299580
Short name T38
Test name
Test status
Simulation time 402870610 ps
CPU time 0.9 seconds
Started Jul 19 04:29:57 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 197992 kb
Host smart-0147d3a0-2292-463c-a1d3-64cf4007bdac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967299580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2967299580
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2635067711
Short name T827
Test name
Test status
Simulation time 27408519 ps
CPU time 0.95 seconds
Started Jul 19 04:29:52 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 198072 kb
Host smart-089e682e-318c-4af5-a2b8-cdda9248606c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635067711 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2635067711
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.270771608
Short name T826
Test name
Test status
Simulation time 16551372 ps
CPU time 0.61 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 195732 kb
Host smart-2ad09bd0-79e7-4812-bee5-fdcb198331dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270771608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.270771608
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.535375674
Short name T774
Test name
Test status
Simulation time 34231967 ps
CPU time 0.66 seconds
Started Jul 19 04:29:53 PM PDT 24
Finished Jul 19 04:30:03 PM PDT 24
Peak memory 193884 kb
Host smart-c198b062-7561-41d6-8aa9-db148c5b7915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535375674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.535375674
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2239425043
Short name T87
Test name
Test status
Simulation time 154095204 ps
CPU time 0.77 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 197096 kb
Host smart-0df26ae1-955b-4284-9108-537dfb9eb1bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239425043 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2239425043
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.55833619
Short name T801
Test name
Test status
Simulation time 490014266 ps
CPU time 2.53 seconds
Started Jul 19 04:29:53 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 198132 kb
Host smart-2781ef87-539e-405e-97b1-4e023654152e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55833619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.55833619
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1008603309
Short name T47
Test name
Test status
Simulation time 86843696 ps
CPU time 0.9 seconds
Started Jul 19 04:29:49 PM PDT 24
Finished Jul 19 04:29:56 PM PDT 24
Peak memory 197184 kb
Host smart-b0d0bf83-6de8-48e5-8514-9ec7d7dc0da7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008603309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1008603309
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2469736600
Short name T720
Test name
Test status
Simulation time 17310034 ps
CPU time 0.65 seconds
Started Jul 19 04:30:03 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 196940 kb
Host smart-358f1c8d-ab72-4844-bf7c-a8a55a8d7cc8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469736600 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2469736600
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4153874904
Short name T92
Test name
Test status
Simulation time 18057982 ps
CPU time 0.62 seconds
Started Jul 19 04:30:02 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 194992 kb
Host smart-1a6729fd-b0ca-4175-af81-70dd35e43e8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153874904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.4153874904
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2070750897
Short name T790
Test name
Test status
Simulation time 15958384 ps
CPU time 0.62 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 193840 kb
Host smart-b27e96d1-85a3-4bce-be36-848fa33277a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070750897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2070750897
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4266786626
Short name T814
Test name
Test status
Simulation time 273447907 ps
CPU time 0.82 seconds
Started Jul 19 04:29:52 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 196596 kb
Host smart-c533d24d-fd73-41a8-8d73-053db726cba5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266786626 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4266786626
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.99166865
Short name T747
Test name
Test status
Simulation time 34325846 ps
CPU time 1.02 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 198000 kb
Host smart-16fc54d4-dde5-48b5-a04a-1081e0d4c280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99166865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.99166865
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4184296360
Short name T718
Test name
Test status
Simulation time 62960064 ps
CPU time 0.93 seconds
Started Jul 19 04:29:57 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 198076 kb
Host smart-f14bfca3-d430-4d78-b204-28fe1149e188
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184296360 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4184296360
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1009354477
Short name T83
Test name
Test status
Simulation time 19932672 ps
CPU time 0.59 seconds
Started Jul 19 04:29:57 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 194908 kb
Host smart-7ddc3138-6109-4e14-ab33-0743bf174a26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009354477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1009354477
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3157694355
Short name T760
Test name
Test status
Simulation time 55231689 ps
CPU time 0.56 seconds
Started Jul 19 04:29:56 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 193884 kb
Host smart-e588f892-39a2-4cab-9519-ecda08d2bb59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157694355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3157694355
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2691677994
Short name T769
Test name
Test status
Simulation time 31444272 ps
CPU time 0.64 seconds
Started Jul 19 04:30:02 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 194812 kb
Host smart-46bab80a-bd93-4931-b29f-d837375e0114
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691677994 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2691677994
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1794937915
Short name T788
Test name
Test status
Simulation time 322257196 ps
CPU time 2.99 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 198156 kb
Host smart-82e63ca7-3cdb-43c8-8fa9-e1e528424219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794937915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1794937915
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1545520104
Short name T126
Test name
Test status
Simulation time 35010849 ps
CPU time 0.81 seconds
Started Jul 19 04:29:59 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 198000 kb
Host smart-72363a02-5471-4503-a20d-a7ad313f8414
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545520104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1545520104
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3971319584
Short name T792
Test name
Test status
Simulation time 54446414 ps
CPU time 0.87 seconds
Started Jul 19 04:30:01 PM PDT 24
Finished Jul 19 04:30:13 PM PDT 24
Peak memory 198068 kb
Host smart-6fb322fa-d5d1-4919-b060-49af7decc171
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971319584 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3971319584
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2374329877
Short name T727
Test name
Test status
Simulation time 46184921 ps
CPU time 0.6 seconds
Started Jul 19 04:29:59 PM PDT 24
Finished Jul 19 04:30:10 PM PDT 24
Peak memory 194992 kb
Host smart-487c0bc2-45b6-478b-8a93-f16797ebe236
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374329877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2374329877
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.257683137
Short name T777
Test name
Test status
Simulation time 86005081 ps
CPU time 0.56 seconds
Started Jul 19 04:29:58 PM PDT 24
Finished Jul 19 04:30:10 PM PDT 24
Peak memory 193792 kb
Host smart-a5ebf6a1-3ced-4498-89d6-cf3da5e2a97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257683137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.257683137
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.192524212
Short name T115
Test name
Test status
Simulation time 21585666 ps
CPU time 0.69 seconds
Started Jul 19 04:29:58 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 195940 kb
Host smart-17e6f6bb-094d-46f2-9be4-866086ac47e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192524212 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.192524212
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2058831590
Short name T794
Test name
Test status
Simulation time 309187100 ps
CPU time 2.56 seconds
Started Jul 19 04:29:59 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 198172 kb
Host smart-42023dd2-7efd-4050-a4ba-7289612b6723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058831590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2058831590
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2190285644
Short name T767
Test name
Test status
Simulation time 47354588 ps
CPU time 0.94 seconds
Started Jul 19 04:29:59 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 197356 kb
Host smart-a7f4a391-10e0-424c-bd8f-467add313ad0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190285644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2190285644
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1029405239
Short name T839
Test name
Test status
Simulation time 24819712 ps
CPU time 1.1 seconds
Started Jul 19 04:29:56 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 198240 kb
Host smart-6637b038-ad97-4998-88b4-a871ed59a08c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029405239 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1029405239
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3388013714
Short name T749
Test name
Test status
Simulation time 70431542 ps
CPU time 0.56 seconds
Started Jul 19 04:30:01 PM PDT 24
Finished Jul 19 04:30:13 PM PDT 24
Peak memory 194880 kb
Host smart-a640f1a2-920d-4f54-8906-695195d91768
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388013714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3388013714
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3135633477
Short name T816
Test name
Test status
Simulation time 65258562 ps
CPU time 0.58 seconds
Started Jul 19 04:30:05 PM PDT 24
Finished Jul 19 04:30:17 PM PDT 24
Peak memory 193880 kb
Host smart-06674fa5-1da8-4776-b32c-81d21121c416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135633477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3135633477
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.882911151
Short name T828
Test name
Test status
Simulation time 36998051 ps
CPU time 0.83 seconds
Started Jul 19 04:29:58 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 198064 kb
Host smart-cb46ffea-daa1-4ab1-94aa-67dc95f645ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882911151 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.882911151
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.589014664
Short name T783
Test name
Test status
Simulation time 223521609 ps
CPU time 1.01 seconds
Started Jul 19 04:29:58 PM PDT 24
Finished Jul 19 04:30:10 PM PDT 24
Peak memory 197960 kb
Host smart-738fe303-4138-456c-8496-9a628503fdb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589014664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.589014664
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2368789590
Short name T764
Test name
Test status
Simulation time 481218331 ps
CPU time 1.37 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 198220 kb
Host smart-439a089e-a75e-4140-af84-2342390f43da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368789590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2368789590
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3615478790
Short name T724
Test name
Test status
Simulation time 61536113 ps
CPU time 0.89 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 197996 kb
Host smart-75e61518-3e14-4679-84c5-643e64c2b2f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615478790 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3615478790
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2290987940
Short name T105
Test name
Test status
Simulation time 40029002 ps
CPU time 0.56 seconds
Started Jul 19 04:29:57 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 194808 kb
Host smart-dbd4d595-a348-4542-a11b-652e1c14630d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290987940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2290987940
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1492891825
Short name T773
Test name
Test status
Simulation time 33860821 ps
CPU time 0.61 seconds
Started Jul 19 04:30:01 PM PDT 24
Finished Jul 19 04:30:13 PM PDT 24
Peak memory 193960 kb
Host smart-3e91e1ff-8f5f-4732-ba06-f43945caa196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492891825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1492891825
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2948317994
Short name T86
Test name
Test status
Simulation time 104064935 ps
CPU time 0.74 seconds
Started Jul 19 04:29:57 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 196784 kb
Host smart-a3b8eebf-b245-41e2-942c-cd22803a5b0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948317994 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2948317994
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.331990757
Short name T785
Test name
Test status
Simulation time 244569997 ps
CPU time 2.16 seconds
Started Jul 19 04:30:06 PM PDT 24
Finished Jul 19 04:30:18 PM PDT 24
Peak memory 198100 kb
Host smart-48007ebc-d0d7-40d0-a510-d3fdd14aba86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331990757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.331990757
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4286199596
Short name T766
Test name
Test status
Simulation time 596708322 ps
CPU time 0.81 seconds
Started Jul 19 04:29:57 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 197136 kb
Host smart-ca2afb20-b3a2-4353-a262-59b7d2ca45cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286199596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4286199596
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4200562296
Short name T836
Test name
Test status
Simulation time 22634189 ps
CPU time 0.66 seconds
Started Jul 19 04:30:05 PM PDT 24
Finished Jul 19 04:30:17 PM PDT 24
Peak memory 197368 kb
Host smart-11833850-2495-47a9-9f45-4942fd47ef44
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200562296 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.4200562296
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2553271340
Short name T93
Test name
Test status
Simulation time 27718935 ps
CPU time 0.59 seconds
Started Jul 19 04:29:59 PM PDT 24
Finished Jul 19 04:30:10 PM PDT 24
Peak memory 194704 kb
Host smart-4f44d4ec-9924-4268-96c3-87a7e340984c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553271340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2553271340
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3093410284
Short name T813
Test name
Test status
Simulation time 12295903 ps
CPU time 0.63 seconds
Started Jul 19 04:29:58 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 193872 kb
Host smart-6a3fcf84-97a3-49e5-bafa-32f5fdb1de28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093410284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3093410284
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1707861953
Short name T112
Test name
Test status
Simulation time 26145424 ps
CPU time 0.7 seconds
Started Jul 19 04:29:58 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 195904 kb
Host smart-c8585bce-84fb-44e7-a984-26fd5cbe96bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707861953 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1707861953
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.859819127
Short name T825
Test name
Test status
Simulation time 57791227 ps
CPU time 1.69 seconds
Started Jul 19 04:30:01 PM PDT 24
Finished Jul 19 04:30:13 PM PDT 24
Peak memory 198404 kb
Host smart-db6d9d23-ae26-41b8-9288-63bf0be5dd38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859819127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.859819127
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2768708011
Short name T37
Test name
Test status
Simulation time 136431291 ps
CPU time 0.78 seconds
Started Jul 19 04:29:59 PM PDT 24
Finished Jul 19 04:30:10 PM PDT 24
Peak memory 197012 kb
Host smart-2505b17a-79bb-4ced-b27f-1f17b2a5b912
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768708011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2768708011
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3460980772
Short name T757
Test name
Test status
Simulation time 127903539 ps
CPU time 1.11 seconds
Started Jul 19 04:30:06 PM PDT 24
Finished Jul 19 04:30:18 PM PDT 24
Peak memory 198152 kb
Host smart-35f880c4-469b-460c-91ea-ab58f1ce985e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460980772 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3460980772
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3932565617
Short name T832
Test name
Test status
Simulation time 27081289 ps
CPU time 0.58 seconds
Started Jul 19 04:30:03 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 194680 kb
Host smart-940fc8fa-6316-4742-adf8-d330f7be81e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932565617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3932565617
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1955602868
Short name T743
Test name
Test status
Simulation time 18017024 ps
CPU time 0.62 seconds
Started Jul 19 04:29:57 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 194568 kb
Host smart-90f912ca-c40b-4d3f-a493-7d9552c680a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955602868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1955602868
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.921012306
Short name T113
Test name
Test status
Simulation time 151336745 ps
CPU time 0.85 seconds
Started Jul 19 04:30:02 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 197264 kb
Host smart-3bafb365-c7be-4c01-847f-60f403e3ab93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921012306 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.921012306
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.883914223
Short name T803
Test name
Test status
Simulation time 213978396 ps
CPU time 1.35 seconds
Started Jul 19 04:30:03 PM PDT 24
Finished Jul 19 04:30:15 PM PDT 24
Peak memory 198184 kb
Host smart-fdcf935e-3d51-465c-9493-f565cd629640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883914223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.883914223
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1560347071
Short name T48
Test name
Test status
Simulation time 170895741 ps
CPU time 0.83 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 197276 kb
Host smart-4cb84665-2717-4d3d-bdad-df8683bf05e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560347071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1560347071
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2693348545
Short name T715
Test name
Test status
Simulation time 94719669 ps
CPU time 0.87 seconds
Started Jul 19 04:30:03 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 198072 kb
Host smart-66a8b8cb-adba-4f6b-8183-c8d76a4fbcf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693348545 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2693348545
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1020118920
Short name T104
Test name
Test status
Simulation time 45495069 ps
CPU time 0.63 seconds
Started Jul 19 04:29:59 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 195212 kb
Host smart-8202aebd-4418-451b-b6df-d792667d9e10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020118920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1020118920
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1035617737
Short name T780
Test name
Test status
Simulation time 18943841 ps
CPU time 0.59 seconds
Started Jul 19 04:29:59 PM PDT 24
Finished Jul 19 04:30:10 PM PDT 24
Peak memory 193948 kb
Host smart-2d5c1944-04d0-4441-9be8-3bdca72aed64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035617737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1035617737
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1656595929
Short name T779
Test name
Test status
Simulation time 59002975 ps
CPU time 0.71 seconds
Started Jul 19 04:30:05 PM PDT 24
Finished Jul 19 04:30:16 PM PDT 24
Peak memory 196184 kb
Host smart-935c0ebf-e7a1-4407-9017-b1b756f3f709
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656595929 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1656595929
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2655813241
Short name T746
Test name
Test status
Simulation time 56718347 ps
CPU time 1.56 seconds
Started Jul 19 04:29:59 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 198140 kb
Host smart-25cbf4eb-c2bf-4b97-a48a-56280c0907da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655813241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2655813241
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.769142297
Short name T820
Test name
Test status
Simulation time 92249979 ps
CPU time 1.13 seconds
Started Jul 19 04:30:06 PM PDT 24
Finished Jul 19 04:30:17 PM PDT 24
Peak memory 197612 kb
Host smart-41495086-e189-4b95-adf0-50ba38bea278
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769142297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.769142297
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3486794086
Short name T807
Test name
Test status
Simulation time 78466715 ps
CPU time 0.72 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:29:53 PM PDT 24
Peak memory 195880 kb
Host smart-728279c9-714e-4811-a1e3-d76a362bbaea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486794086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3486794086
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3439754986
Short name T739
Test name
Test status
Simulation time 293103008 ps
CPU time 2.95 seconds
Started Jul 19 04:29:53 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 198124 kb
Host smart-9f724ad7-d066-4cb8-bb19-221a0c08d141
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439754986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3439754986
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.686288844
Short name T762
Test name
Test status
Simulation time 63529386 ps
CPU time 0.69 seconds
Started Jul 19 04:29:48 PM PDT 24
Finished Jul 19 04:29:55 PM PDT 24
Peak memory 191620 kb
Host smart-9790e395-c0b7-4c46-8662-228a1660fb81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686288844 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.686288844
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1754019152
Short name T735
Test name
Test status
Simulation time 12614584 ps
CPU time 0.59 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:29:44 PM PDT 24
Peak memory 195472 kb
Host smart-7774daaa-30c6-4a24-a9d3-0750b4afae0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754019152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1754019152
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1497763675
Short name T725
Test name
Test status
Simulation time 13544808 ps
CPU time 0.57 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:29:45 PM PDT 24
Peak memory 193852 kb
Host smart-c230187f-cdfa-4713-a95b-85344970e3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497763675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1497763675
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4067504616
Short name T821
Test name
Test status
Simulation time 141824555 ps
CPU time 0.83 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 197080 kb
Host smart-098eeb96-bd39-47e1-af82-c4bfb4f7af4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067504616 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4067504616
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1886646921
Short name T812
Test name
Test status
Simulation time 171039305 ps
CPU time 2.41 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:29:55 PM PDT 24
Peak memory 198136 kb
Host smart-591ce74b-03ff-4746-a296-f6f526e03536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886646921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1886646921
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2102833493
Short name T804
Test name
Test status
Simulation time 403311211 ps
CPU time 1.1 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 198132 kb
Host smart-9df91a84-adc8-42c9-897f-f2b9837e18e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102833493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2102833493
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.4114747531
Short name T834
Test name
Test status
Simulation time 51720239 ps
CPU time 0.61 seconds
Started Jul 19 04:30:06 PM PDT 24
Finished Jul 19 04:30:17 PM PDT 24
Peak memory 194432 kb
Host smart-0bae3608-cd08-44b6-8e96-c725d41d711b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114747531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.4114747531
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.269099161
Short name T802
Test name
Test status
Simulation time 15892248 ps
CPU time 0.6 seconds
Started Jul 19 04:30:02 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 193948 kb
Host smart-2feb3d20-1111-4919-8a7f-647de8e7371d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269099161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.269099161
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.677456758
Short name T818
Test name
Test status
Simulation time 12694592 ps
CPU time 0.55 seconds
Started Jul 19 04:30:05 PM PDT 24
Finished Jul 19 04:30:16 PM PDT 24
Peak memory 193764 kb
Host smart-c7626a8b-db70-464d-9105-3797d5ba5314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677456758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.677456758
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1461488353
Short name T741
Test name
Test status
Simulation time 65546949 ps
CPU time 0.6 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 193960 kb
Host smart-4922902c-8993-4680-a2c9-a7ce89788f3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461488353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1461488353
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.4032937087
Short name T756
Test name
Test status
Simulation time 26138255 ps
CPU time 0.59 seconds
Started Jul 19 04:30:09 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 194464 kb
Host smart-6a0f94fa-8e8c-44f4-a5ce-d4d013c4d39e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032937087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.4032937087
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2330158739
Short name T728
Test name
Test status
Simulation time 99143699 ps
CPU time 0.56 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 193840 kb
Host smart-9070bf03-cf76-4c8f-9d19-6cec3292d00e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330158739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2330158739
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1896574499
Short name T754
Test name
Test status
Simulation time 31881574 ps
CPU time 0.6 seconds
Started Jul 19 04:30:10 PM PDT 24
Finished Jul 19 04:30:20 PM PDT 24
Peak memory 193892 kb
Host smart-dfee7fda-fa50-4520-a91f-492be1e41a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896574499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1896574499
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3514043542
Short name T730
Test name
Test status
Simulation time 16768430 ps
CPU time 0.58 seconds
Started Jul 19 04:30:09 PM PDT 24
Finished Jul 19 04:30:20 PM PDT 24
Peak memory 193844 kb
Host smart-f2027f8e-63e3-4539-b9e6-3bebb5e580b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514043542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3514043542
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3328660430
Short name T791
Test name
Test status
Simulation time 25415178 ps
CPU time 0.6 seconds
Started Jul 19 04:30:12 PM PDT 24
Finished Jul 19 04:30:21 PM PDT 24
Peak memory 193868 kb
Host smart-efe81e42-f166-410d-be35-52ddf1f78eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328660430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3328660430
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1927580849
Short name T771
Test name
Test status
Simulation time 20364974 ps
CPU time 0.57 seconds
Started Jul 19 04:30:13 PM PDT 24
Finished Jul 19 04:30:22 PM PDT 24
Peak memory 193840 kb
Host smart-3bc192ad-6580-4af4-9531-10666768dd06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927580849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1927580849
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2000844269
Short name T823
Test name
Test status
Simulation time 21302149 ps
CPU time 0.7 seconds
Started Jul 19 04:30:04 PM PDT 24
Finished Jul 19 04:30:16 PM PDT 24
Peak memory 194592 kb
Host smart-7e3dd6c9-498f-432d-92a7-62f8e565aefd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000844269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2000844269
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.391472980
Short name T786
Test name
Test status
Simulation time 48755697 ps
CPU time 1.27 seconds
Started Jul 19 04:29:52 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 196988 kb
Host smart-f5562507-529b-4cdd-88b1-37cf76e746ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391472980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.391472980
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1303902879
Short name T765
Test name
Test status
Simulation time 39204830 ps
CPU time 0.6 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 194860 kb
Host smart-910884c1-f59e-4bae-9f4a-9209acfd2457
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303902879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1303902879
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3295948601
Short name T793
Test name
Test status
Simulation time 43450195 ps
CPU time 1.43 seconds
Started Jul 19 04:29:48 PM PDT 24
Finished Jul 19 04:29:56 PM PDT 24
Peak memory 198192 kb
Host smart-84375781-2c1f-4637-acc4-65e6aed011d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295948601 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3295948601
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3981782930
Short name T91
Test name
Test status
Simulation time 12489258 ps
CPU time 0.57 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 194064 kb
Host smart-663e8583-9c49-4a6c-876a-08e0443c580d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981782930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3981782930
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2033191127
Short name T778
Test name
Test status
Simulation time 11031511 ps
CPU time 0.57 seconds
Started Jul 19 04:29:54 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 193644 kb
Host smart-d1c836f9-81ae-4989-b4b0-b18e607648c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033191127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2033191127
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2700195606
Short name T829
Test name
Test status
Simulation time 356320805 ps
CPU time 0.86 seconds
Started Jul 19 04:29:51 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 197580 kb
Host smart-4a0cb4dd-2534-4982-be11-ad697b3bf41a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700195606 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2700195606
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.4147276454
Short name T781
Test name
Test status
Simulation time 99004953 ps
CPU time 1.33 seconds
Started Jul 19 04:29:49 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 198192 kb
Host smart-d339bb94-8fee-4f55-b5ba-ccd1962c2f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147276454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.4147276454
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3381957841
Short name T805
Test name
Test status
Simulation time 222105962 ps
CPU time 1.37 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 198020 kb
Host smart-b2c51131-7d9e-45bc-8d31-372d6c14d41e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381957841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3381957841
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3726016847
Short name T768
Test name
Test status
Simulation time 15583880 ps
CPU time 0.58 seconds
Started Jul 19 04:30:09 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 193864 kb
Host smart-da8babd9-fece-4337-ac4e-c88bf227cc6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726016847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3726016847
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2342827306
Short name T758
Test name
Test status
Simulation time 29320492 ps
CPU time 0.59 seconds
Started Jul 19 04:30:10 PM PDT 24
Finished Jul 19 04:30:20 PM PDT 24
Peak memory 193888 kb
Host smart-df8a55a7-396e-4e6f-930d-54d461d2c397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342827306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2342827306
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1790362767
Short name T721
Test name
Test status
Simulation time 61235204 ps
CPU time 0.57 seconds
Started Jul 19 04:30:11 PM PDT 24
Finished Jul 19 04:30:21 PM PDT 24
Peak memory 193848 kb
Host smart-7493faae-32b2-471e-9f93-e249d673d6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790362767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1790362767
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2243723979
Short name T744
Test name
Test status
Simulation time 29512670 ps
CPU time 0.6 seconds
Started Jul 19 04:30:07 PM PDT 24
Finished Jul 19 04:30:18 PM PDT 24
Peak memory 193964 kb
Host smart-f84b96e4-e888-4b41-a290-1b31a06ba8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243723979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2243723979
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.688795927
Short name T797
Test name
Test status
Simulation time 17031534 ps
CPU time 0.59 seconds
Started Jul 19 04:30:11 PM PDT 24
Finished Jul 19 04:30:21 PM PDT 24
Peak memory 194532 kb
Host smart-27273f0d-0c0a-415a-bfb1-308a0c43e125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688795927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.688795927
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.386011293
Short name T830
Test name
Test status
Simulation time 83985056 ps
CPU time 0.62 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 193868 kb
Host smart-9cbbb1c5-ed5b-49f9-97d3-f855e4f1793c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386011293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.386011293
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.187844492
Short name T740
Test name
Test status
Simulation time 24053494 ps
CPU time 0.58 seconds
Started Jul 19 04:30:10 PM PDT 24
Finished Jul 19 04:30:20 PM PDT 24
Peak memory 193800 kb
Host smart-5b197bbf-a020-4ed7-9e1f-952910b20749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187844492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.187844492
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2453427091
Short name T817
Test name
Test status
Simulation time 98968253 ps
CPU time 0.54 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 193848 kb
Host smart-4a2468d7-6fc6-4e79-972d-286cfc497330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453427091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2453427091
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2897762148
Short name T787
Test name
Test status
Simulation time 16018098 ps
CPU time 0.57 seconds
Started Jul 19 04:30:10 PM PDT 24
Finished Jul 19 04:30:20 PM PDT 24
Peak memory 193868 kb
Host smart-971fabde-92a3-45d8-af12-abb381587c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897762148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2897762148
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2562483520
Short name T731
Test name
Test status
Simulation time 41832019 ps
CPU time 0.54 seconds
Started Jul 19 04:30:10 PM PDT 24
Finished Jul 19 04:30:20 PM PDT 24
Peak memory 193844 kb
Host smart-071a5287-f59f-415a-8bc8-0702dcee4889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562483520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2562483520
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.4054483554
Short name T107
Test name
Test status
Simulation time 65193093 ps
CPU time 0.62 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 195028 kb
Host smart-eef03e28-ad64-4f02-b00e-6ce54e311669
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054483554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.4054483554
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1520860409
Short name T806
Test name
Test status
Simulation time 59162721 ps
CPU time 2.12 seconds
Started Jul 19 04:29:49 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 197204 kb
Host smart-b2f1a235-823e-4ffa-825d-01b7f3a3f666
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520860409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1520860409
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1845639160
Short name T759
Test name
Test status
Simulation time 67046995 ps
CPU time 0.62 seconds
Started Jul 19 04:29:52 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 195416 kb
Host smart-2a0b0e9e-432a-4da5-bf97-f42ea1db4673
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845639160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1845639160
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2030680268
Short name T838
Test name
Test status
Simulation time 42813206 ps
CPU time 1.17 seconds
Started Jul 19 04:29:56 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 198240 kb
Host smart-ff16cafe-e552-438b-9a93-5b7773dddd53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030680268 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2030680268
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.305136528
Short name T90
Test name
Test status
Simulation time 13688381 ps
CPU time 0.57 seconds
Started Jul 19 04:29:57 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 193780 kb
Host smart-1351a888-2df7-4435-bdc7-e544967e1601
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305136528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.305136528
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.8416426
Short name T822
Test name
Test status
Simulation time 12040785 ps
CPU time 0.56 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 193776 kb
Host smart-bb4a2f3b-085a-4a5c-8313-0f9ccb29dbf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8416426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.8416426
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.824138181
Short name T84
Test name
Test status
Simulation time 16895048 ps
CPU time 0.77 seconds
Started Jul 19 04:29:56 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 196180 kb
Host smart-80b488c0-344f-429d-98a0-127fc6cfb229
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824138181 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.824138181
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.408478596
Short name T716
Test name
Test status
Simulation time 76059511 ps
CPU time 0.97 seconds
Started Jul 19 04:29:49 PM PDT 24
Finished Jul 19 04:29:56 PM PDT 24
Peak memory 198000 kb
Host smart-6119f80a-421d-4e6a-9bf9-9b3241fadb59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408478596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.408478596
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3639646459
Short name T127
Test name
Test status
Simulation time 431618480 ps
CPU time 1.38 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 198264 kb
Host smart-dca46778-2614-477a-b8c2-6d393c0dd18a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639646459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3639646459
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3273896418
Short name T831
Test name
Test status
Simulation time 58537833 ps
CPU time 0.57 seconds
Started Jul 19 04:30:11 PM PDT 24
Finished Jul 19 04:30:21 PM PDT 24
Peak memory 193808 kb
Host smart-04482830-85c2-49cd-a005-2a4906f6950d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273896418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3273896418
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3950174077
Short name T784
Test name
Test status
Simulation time 43257196 ps
CPU time 0.66 seconds
Started Jul 19 04:30:09 PM PDT 24
Finished Jul 19 04:30:20 PM PDT 24
Peak memory 194568 kb
Host smart-5df54bc2-2089-41d4-b464-ef88ee5933d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950174077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3950174077
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.4277279472
Short name T770
Test name
Test status
Simulation time 42067068 ps
CPU time 0.59 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 193888 kb
Host smart-801ead54-7421-476f-b832-c12406ae4644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277279472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.4277279472
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1702353250
Short name T717
Test name
Test status
Simulation time 47769909 ps
CPU time 0.58 seconds
Started Jul 19 04:30:11 PM PDT 24
Finished Jul 19 04:30:21 PM PDT 24
Peak memory 193860 kb
Host smart-094bd17e-ee4e-4abe-847d-94c7548b48d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702353250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1702353250
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3039615534
Short name T763
Test name
Test status
Simulation time 47004743 ps
CPU time 0.56 seconds
Started Jul 19 04:30:10 PM PDT 24
Finished Jul 19 04:30:20 PM PDT 24
Peak memory 193840 kb
Host smart-5a3002b6-e36e-481f-aad2-1a09f31992a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039615534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3039615534
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3490701017
Short name T753
Test name
Test status
Simulation time 61505114 ps
CPU time 0.58 seconds
Started Jul 19 04:30:13 PM PDT 24
Finished Jul 19 04:30:23 PM PDT 24
Peak memory 193960 kb
Host smart-bcf0b689-4526-48ce-bad9-739316d49462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490701017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3490701017
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.162600695
Short name T713
Test name
Test status
Simulation time 31898406 ps
CPU time 0.56 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 193852 kb
Host smart-144a55b5-a9c8-44b5-9c4e-21b398c4c723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162600695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.162600695
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.260324318
Short name T840
Test name
Test status
Simulation time 11929016 ps
CPU time 0.55 seconds
Started Jul 19 04:30:09 PM PDT 24
Finished Jul 19 04:30:20 PM PDT 24
Peak memory 193880 kb
Host smart-556f2129-c93b-43c4-8e8b-395d502166cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260324318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.260324318
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3559707152
Short name T772
Test name
Test status
Simulation time 17365005 ps
CPU time 0.63 seconds
Started Jul 19 04:30:11 PM PDT 24
Finished Jul 19 04:30:21 PM PDT 24
Peak memory 194536 kb
Host smart-2806c3d0-86e3-49c5-9df9-17c290b2f589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559707152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3559707152
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.314106874
Short name T809
Test name
Test status
Simulation time 17156110 ps
CPU time 0.63 seconds
Started Jul 19 04:30:12 PM PDT 24
Finished Jul 19 04:30:21 PM PDT 24
Peak memory 194740 kb
Host smart-fdd85622-006b-45c5-9d8c-4f6d1ea6849a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314106874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.314106874
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2704565845
Short name T742
Test name
Test status
Simulation time 25605885 ps
CPU time 0.89 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 198052 kb
Host smart-a24be24a-43d0-4950-a7dc-397558dc688d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704565845 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2704565845
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3784897124
Short name T89
Test name
Test status
Simulation time 71375285 ps
CPU time 0.57 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 193660 kb
Host smart-84dcd5f0-93ab-465d-b7d7-3a8db73ad04b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784897124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3784897124
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3264258651
Short name T835
Test name
Test status
Simulation time 11418289 ps
CPU time 0.58 seconds
Started Jul 19 04:30:03 PM PDT 24
Finished Jul 19 04:30:15 PM PDT 24
Peak memory 193840 kb
Host smart-1a07796b-5fdb-47a9-a783-a012a87f82e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264258651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3264258651
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.348893114
Short name T808
Test name
Test status
Simulation time 209728399 ps
CPU time 0.81 seconds
Started Jul 19 04:29:56 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 196224 kb
Host smart-bbe9acd1-9c95-4aa6-b582-573ef7d97279
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348893114 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.348893114
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.894861558
Short name T748
Test name
Test status
Simulation time 89547730 ps
CPU time 1.18 seconds
Started Jul 19 04:30:03 PM PDT 24
Finished Jul 19 04:30:15 PM PDT 24
Peak memory 198164 kb
Host smart-0eb6c8f0-3593-4b8e-8044-ff9672c5010d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894861558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.894861558
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3579181264
Short name T50
Test name
Test status
Simulation time 41482180 ps
CPU time 0.83 seconds
Started Jul 19 04:29:49 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 198048 kb
Host smart-5cd97fc6-a935-43b6-a770-35b11e24f47e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579181264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3579181264
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2116354387
Short name T745
Test name
Test status
Simulation time 30011713 ps
CPU time 0.83 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 198052 kb
Host smart-c5f25baf-4139-4960-a8d7-692a250af73c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116354387 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2116354387
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.922699780
Short name T734
Test name
Test status
Simulation time 13709691 ps
CPU time 0.6 seconds
Started Jul 19 04:29:48 PM PDT 24
Finished Jul 19 04:29:56 PM PDT 24
Peak memory 195544 kb
Host smart-e799aa4a-2956-438d-9b7d-360ca7127021
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922699780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.922699780
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3624825108
Short name T751
Test name
Test status
Simulation time 94786005 ps
CPU time 0.61 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 193844 kb
Host smart-a7a21e6c-f17d-4387-836a-cdab886b19da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624825108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3624825108
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3381167476
Short name T88
Test name
Test status
Simulation time 62313299 ps
CPU time 0.73 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 196072 kb
Host smart-99500665-4a8a-49e6-82ed-54a7e75b0acd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381167476 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3381167476
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.884902612
Short name T776
Test name
Test status
Simulation time 36896308 ps
CPU time 1.07 seconds
Started Jul 19 04:29:52 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 197984 kb
Host smart-3997b1c8-bb68-44ec-98e5-f4fbd64d719c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884902612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.884902612
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.590468824
Short name T49
Test name
Test status
Simulation time 430675454 ps
CPU time 1.37 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 198164 kb
Host smart-d4a45e1a-e488-4522-98b2-a86379a0ac35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590468824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.590468824
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3519675988
Short name T722
Test name
Test status
Simulation time 77268986 ps
CPU time 1.07 seconds
Started Jul 19 04:29:52 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 198044 kb
Host smart-b4153546-95ca-48e4-a148-117832739cd4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519675988 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3519675988
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2326039625
Short name T811
Test name
Test status
Simulation time 14925308 ps
CPU time 0.64 seconds
Started Jul 19 04:29:51 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 195580 kb
Host smart-85394eb0-37fe-465b-aee8-3b5f74e53854
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326039625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2326039625
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1716151481
Short name T752
Test name
Test status
Simulation time 14965313 ps
CPU time 0.57 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:29:54 PM PDT 24
Peak memory 194584 kb
Host smart-61b9fb07-dc5e-4b7f-8d2f-8052f228d4a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716151481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1716151481
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4012971483
Short name T114
Test name
Test status
Simulation time 55163405 ps
CPU time 0.75 seconds
Started Jul 19 04:29:51 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 196280 kb
Host smart-2f4692ff-1bd9-4b1d-b1b7-889b44800b86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012971483 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.4012971483
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2398508738
Short name T819
Test name
Test status
Simulation time 687795160 ps
CPU time 1.57 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 198156 kb
Host smart-85132a3d-ba01-4a94-8c48-13a149957221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398508738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2398508738
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.145423339
Short name T800
Test name
Test status
Simulation time 510926565 ps
CPU time 1.44 seconds
Started Jul 19 04:29:54 PM PDT 24
Finished Jul 19 04:30:05 PM PDT 24
Peak memory 198044 kb
Host smart-1c450b49-a8dc-4453-9002-33035258fe07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145423339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.145423339
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3942140298
Short name T737
Test name
Test status
Simulation time 65462262 ps
CPU time 0.78 seconds
Started Jul 19 04:29:52 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 198072 kb
Host smart-8da4dddc-ec2d-4456-b721-b83767eb1a9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942140298 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3942140298
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2072318245
Short name T729
Test name
Test status
Simulation time 27161081 ps
CPU time 0.6 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 195372 kb
Host smart-cdd2a0ed-4a72-4499-a88f-9123464b32d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072318245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2072318245
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.230617788
Short name T719
Test name
Test status
Simulation time 23387041 ps
CPU time 0.58 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 193812 kb
Host smart-efe08b61-6396-4ef1-957b-fa20c9427fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230617788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.230617788
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1362790292
Short name T755
Test name
Test status
Simulation time 17360707 ps
CPU time 0.67 seconds
Started Jul 19 04:29:51 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 194904 kb
Host smart-d776199a-b5cd-4fe8-92b7-61952cdf8504
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362790292 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1362790292
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1615571438
Short name T796
Test name
Test status
Simulation time 59642130 ps
CPU time 1.42 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 198084 kb
Host smart-390853cd-3986-4693-bbe9-b12ab2d03f61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615571438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1615571438
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.39640485
Short name T733
Test name
Test status
Simulation time 66413247 ps
CPU time 1.56 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 197904 kb
Host smart-522ae932-1e06-44ec-88a8-a91510caab3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39640485 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.39640485
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.374184892
Short name T810
Test name
Test status
Simulation time 41641640 ps
CPU time 0.6 seconds
Started Jul 19 04:29:57 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 194112 kb
Host smart-dbd28b1f-1333-47e1-b0bd-857f665b4b66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374184892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.374184892
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1387080663
Short name T726
Test name
Test status
Simulation time 50348296 ps
CPU time 0.57 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 194464 kb
Host smart-4558459e-15bd-4054-94ca-28f217691557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387080663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1387080663
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2707524478
Short name T782
Test name
Test status
Simulation time 21440125 ps
CPU time 0.64 seconds
Started Jul 19 04:29:52 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 194884 kb
Host smart-2eeb4e93-4445-4935-b334-70f5efba042e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707524478 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2707524478
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.344151522
Short name T723
Test name
Test status
Simulation time 123097472 ps
CPU time 1.59 seconds
Started Jul 19 04:30:00 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 198164 kb
Host smart-cfe0612b-1a6a-4d26-ab4f-aa32279f1130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344151522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.344151522
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2750805153
Short name T45
Test name
Test status
Simulation time 401184105 ps
CPU time 1.32 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 198172 kb
Host smart-d817d809-d36c-4848-9f2e-fc8bae6689c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750805153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2750805153
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2389381868
Short name T28
Test name
Test status
Simulation time 13922503 ps
CPU time 0.61 seconds
Started Jul 19 04:43:06 PM PDT 24
Finished Jul 19 04:43:07 PM PDT 24
Peak memory 196000 kb
Host smart-0e8c5f2c-8467-4a5a-83c8-ebe4e2ae6eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389381868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2389381868
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3394391828
Short name T518
Test name
Test status
Simulation time 244549843 ps
CPU time 0.74 seconds
Started Jul 19 04:43:08 PM PDT 24
Finished Jul 19 04:43:10 PM PDT 24
Peak memory 196236 kb
Host smart-ebb4f75c-6d33-4ad4-85ea-026b65fa1939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394391828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3394391828
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.737909292
Short name T451
Test name
Test status
Simulation time 283692680 ps
CPU time 8.21 seconds
Started Jul 19 04:43:07 PM PDT 24
Finished Jul 19 04:43:16 PM PDT 24
Peak memory 197136 kb
Host smart-0ebf92a5-831c-48cd-8dbc-f712ee8201f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737909292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.737909292
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1582838901
Short name T565
Test name
Test status
Simulation time 84632765 ps
CPU time 1.01 seconds
Started Jul 19 04:43:07 PM PDT 24
Finished Jul 19 04:43:09 PM PDT 24
Peak memory 196868 kb
Host smart-b8366701-3bc2-4710-b607-50030bf97863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582838901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1582838901
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2404638202
Short name T419
Test name
Test status
Simulation time 269352944 ps
CPU time 1.17 seconds
Started Jul 19 04:43:06 PM PDT 24
Finished Jul 19 04:43:08 PM PDT 24
Peak memory 196212 kb
Host smart-533cecde-48b3-4657-bdac-de43a2a1c51d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404638202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2404638202
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.382201374
Short name T384
Test name
Test status
Simulation time 164172453 ps
CPU time 1.66 seconds
Started Jul 19 04:43:05 PM PDT 24
Finished Jul 19 04:43:07 PM PDT 24
Peak memory 197432 kb
Host smart-e2a9b08f-0640-4a0f-afbc-244941daa922
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382201374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.382201374
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1692109374
Short name T614
Test name
Test status
Simulation time 111086658 ps
CPU time 2.56 seconds
Started Jul 19 04:43:14 PM PDT 24
Finished Jul 19 04:43:19 PM PDT 24
Peak memory 197228 kb
Host smart-d21ee92d-c91e-4faa-b40a-e757cc9122ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692109374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1692109374
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3144493285
Short name T349
Test name
Test status
Simulation time 22726490 ps
CPU time 0.92 seconds
Started Jul 19 04:43:23 PM PDT 24
Finished Jul 19 04:43:26 PM PDT 24
Peak memory 196764 kb
Host smart-e2413255-28ff-4d15-a618-ffe7ba4c695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144493285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3144493285
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2015938099
Short name T330
Test name
Test status
Simulation time 112341702 ps
CPU time 0.85 seconds
Started Jul 19 04:43:09 PM PDT 24
Finished Jul 19 04:43:11 PM PDT 24
Peak memory 196556 kb
Host smart-930ffbf7-2082-417e-9c0e-a197ac8438a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015938099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2015938099
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.95066560
Short name T644
Test name
Test status
Simulation time 1489254361 ps
CPU time 6.08 seconds
Started Jul 19 04:43:11 PM PDT 24
Finished Jul 19 04:43:18 PM PDT 24
Peak memory 198168 kb
Host smart-6cdeaec1-eaee-4300-ac25-7f0006d77a40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95066560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rando
m_long_reg_writes_reg_reads.95066560
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.4201659681
Short name T75
Test name
Test status
Simulation time 53973389 ps
CPU time 1.1 seconds
Started Jul 19 04:43:16 PM PDT 24
Finished Jul 19 04:43:19 PM PDT 24
Peak memory 195768 kb
Host smart-d75d7f51-315e-4629-8eeb-a427e9a0eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201659681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.4201659681
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1363970391
Short name T338
Test name
Test status
Simulation time 126012406 ps
CPU time 1.21 seconds
Started Jul 19 04:43:10 PM PDT 24
Finished Jul 19 04:43:12 PM PDT 24
Peak memory 196448 kb
Host smart-8b758514-2d7d-4b62-99d5-5ca166adccdc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363970391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1363970391
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1340257128
Short name T543
Test name
Test status
Simulation time 8006259236 ps
CPU time 55.54 seconds
Started Jul 19 04:43:15 PM PDT 24
Finished Jul 19 04:44:13 PM PDT 24
Peak memory 198260 kb
Host smart-210ca36e-cc0d-4cab-b529-cebbe42cfed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340257128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1340257128
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1613014006
Short name T273
Test name
Test status
Simulation time 15548551 ps
CPU time 0.55 seconds
Started Jul 19 04:43:18 PM PDT 24
Finished Jul 19 04:43:21 PM PDT 24
Peak memory 194820 kb
Host smart-204cf6bb-263c-4b52-ab22-1f2d16a21598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613014006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1613014006
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1309809870
Short name T674
Test name
Test status
Simulation time 58113834 ps
CPU time 0.98 seconds
Started Jul 19 04:43:22 PM PDT 24
Finished Jul 19 04:43:25 PM PDT 24
Peak memory 196100 kb
Host smart-660fabc6-116d-4c8a-a674-8b029d272684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309809870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1309809870
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1779428375
Short name T264
Test name
Test status
Simulation time 260910780 ps
CPU time 8.18 seconds
Started Jul 19 04:43:18 PM PDT 24
Finished Jul 19 04:43:29 PM PDT 24
Peak memory 197064 kb
Host smart-b25c57dc-c5e3-484f-9752-3a6971efcc1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779428375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1779428375
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1562999502
Short name T360
Test name
Test status
Simulation time 35023421 ps
CPU time 0.64 seconds
Started Jul 19 04:43:21 PM PDT 24
Finished Jul 19 04:43:25 PM PDT 24
Peak memory 194668 kb
Host smart-e4152b88-eab4-4ea2-a79c-4ded91b7dbe3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562999502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1562999502
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1926676090
Short name T526
Test name
Test status
Simulation time 224140039 ps
CPU time 1.05 seconds
Started Jul 19 04:43:09 PM PDT 24
Finished Jul 19 04:43:11 PM PDT 24
Peak memory 196344 kb
Host smart-bd4207fe-fec2-497e-b9b4-9133429435d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926676090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1926676090
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.952410434
Short name T21
Test name
Test status
Simulation time 334692676 ps
CPU time 3.19 seconds
Started Jul 19 04:43:06 PM PDT 24
Finished Jul 19 04:43:10 PM PDT 24
Peak memory 198236 kb
Host smart-5025cf0c-26f2-4b35-b1b8-f8d17e05e529
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952410434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.952410434
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2445702954
Short name T646
Test name
Test status
Simulation time 156611693 ps
CPU time 1.02 seconds
Started Jul 19 04:43:04 PM PDT 24
Finished Jul 19 04:43:06 PM PDT 24
Peak memory 196332 kb
Host smart-3a30ca33-347a-4fca-bde3-2bcb5f5e75ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445702954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2445702954
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3478576528
Short name T231
Test name
Test status
Simulation time 31790053 ps
CPU time 0.86 seconds
Started Jul 19 04:43:14 PM PDT 24
Finished Jul 19 04:43:17 PM PDT 24
Peak memory 196800 kb
Host smart-33523699-cc2b-4d47-b8ed-386e10d98bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478576528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3478576528
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.4256048945
Short name T579
Test name
Test status
Simulation time 18798042 ps
CPU time 0.82 seconds
Started Jul 19 04:43:21 PM PDT 24
Finished Jul 19 04:43:25 PM PDT 24
Peak memory 197440 kb
Host smart-43ac15db-f1e2-4469-b99e-c3698846926d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256048945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.4256048945
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.218396596
Short name T532
Test name
Test status
Simulation time 83863388 ps
CPU time 1.79 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:33 PM PDT 24
Peak memory 198152 kb
Host smart-55ebca29-7a92-4330-aace-0c9685e46ea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218396596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.218396596
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.4273986812
Short name T51
Test name
Test status
Simulation time 59228742 ps
CPU time 0.8 seconds
Started Jul 19 04:43:15 PM PDT 24
Finished Jul 19 04:43:17 PM PDT 24
Peak memory 214216 kb
Host smart-ab6e1afd-5bcb-4b4c-be90-1823b5119a56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273986812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.4273986812
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3907899049
Short name T414
Test name
Test status
Simulation time 45179002 ps
CPU time 1.25 seconds
Started Jul 19 04:43:09 PM PDT 24
Finished Jul 19 04:43:11 PM PDT 24
Peak memory 196716 kb
Host smart-dcdccaa2-b006-476b-af16-2f619b7ced70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907899049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3907899049
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3341809737
Short name T169
Test name
Test status
Simulation time 1216690823 ps
CPU time 1.07 seconds
Started Jul 19 04:43:10 PM PDT 24
Finished Jul 19 04:43:12 PM PDT 24
Peak memory 195888 kb
Host smart-5e19a107-90f4-4001-b7ab-da8dcc53fade
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341809737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3341809737
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.924718454
Short name T441
Test name
Test status
Simulation time 45584385433 ps
CPU time 119.07 seconds
Started Jul 19 04:43:15 PM PDT 24
Finished Jul 19 04:45:16 PM PDT 24
Peak memory 198336 kb
Host smart-98a9e763-276f-49e7-bd82-38d779c4877d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924718454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.924718454
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2467227225
Short name T616
Test name
Test status
Simulation time 16232763 ps
CPU time 0.59 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:36 PM PDT 24
Peak memory 194220 kb
Host smart-4ca49dd9-940c-4836-9627-63cb380f2ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467227225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2467227225
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1378185883
Short name T686
Test name
Test status
Simulation time 77924119 ps
CPU time 0.88 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:39 PM PDT 24
Peak memory 197424 kb
Host smart-83aa5854-bca9-47b5-80e2-e562921f4a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378185883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1378185883
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1470609488
Short name T268
Test name
Test status
Simulation time 1417245413 ps
CPU time 22.53 seconds
Started Jul 19 04:43:31 PM PDT 24
Finished Jul 19 04:44:01 PM PDT 24
Peak memory 195764 kb
Host smart-6eee4243-2520-4fce-9981-fd9d546e04a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470609488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1470609488
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1855526071
Short name T305
Test name
Test status
Simulation time 69509414 ps
CPU time 1 seconds
Started Jul 19 04:43:32 PM PDT 24
Finished Jul 19 04:43:40 PM PDT 24
Peak memory 198052 kb
Host smart-e074f40c-dbab-4936-9b99-420a63f7dda3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855526071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1855526071
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4220783026
Short name T425
Test name
Test status
Simulation time 138132382 ps
CPU time 1.23 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 197336 kb
Host smart-33220814-f234-46cc-bc32-a4616a81201a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220783026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4220783026
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1106747682
Short name T252
Test name
Test status
Simulation time 152057994 ps
CPU time 2.89 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:40 PM PDT 24
Peak memory 198240 kb
Host smart-6e2ed544-adb8-4800-8013-e0a74fdc754d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106747682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1106747682
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2155226630
Short name T639
Test name
Test status
Simulation time 165724406 ps
CPU time 1.78 seconds
Started Jul 19 04:43:31 PM PDT 24
Finished Jul 19 04:43:40 PM PDT 24
Peak memory 196388 kb
Host smart-1665ccd6-e8e0-4599-a34f-23c365a6a332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155226630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2155226630
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3882031657
Short name T471
Test name
Test status
Simulation time 46569884 ps
CPU time 0.98 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:37 PM PDT 24
Peak memory 196900 kb
Host smart-165fe38f-9754-4f31-8c95-10d6204b5271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882031657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3882031657
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1910634011
Short name T355
Test name
Test status
Simulation time 71831727 ps
CPU time 1.18 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:37 PM PDT 24
Peak memory 197236 kb
Host smart-7303d16a-ca60-445b-82f6-a19c179a5652
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910634011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1910634011
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1860669333
Short name T245
Test name
Test status
Simulation time 247794459 ps
CPU time 1.7 seconds
Started Jul 19 04:43:32 PM PDT 24
Finished Jul 19 04:43:41 PM PDT 24
Peak memory 198240 kb
Host smart-82bc99b0-93c9-442b-b4b4-af40e351889e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860669333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1860669333
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2817890177
Short name T380
Test name
Test status
Simulation time 31817831 ps
CPU time 0.93 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:35 PM PDT 24
Peak memory 195980 kb
Host smart-1f6e792c-48f4-41e4-9e25-0e2b59cdaceb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817890177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2817890177
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2679715267
Short name T12
Test name
Test status
Simulation time 4734956010 ps
CPU time 31.23 seconds
Started Jul 19 04:43:33 PM PDT 24
Finished Jul 19 04:44:12 PM PDT 24
Peak memory 198300 kb
Host smart-fdbed028-56e2-446a-a488-d3128126b00d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679715267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2679715267
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1314409633
Short name T162
Test name
Test status
Simulation time 13935580 ps
CPU time 0.57 seconds
Started Jul 19 04:43:37 PM PDT 24
Finished Jul 19 04:43:44 PM PDT 24
Peak memory 194200 kb
Host smart-f9f3a6b3-42a1-4123-a87b-c76e2d5f5232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314409633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1314409633
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2029381297
Short name T238
Test name
Test status
Simulation time 22879217 ps
CPU time 0.65 seconds
Started Jul 19 04:43:35 PM PDT 24
Finished Jul 19 04:43:42 PM PDT 24
Peak memory 194292 kb
Host smart-1b700b39-0fea-49a4-9e70-2d5f4d015901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029381297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2029381297
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1503161009
Short name T258
Test name
Test status
Simulation time 835840028 ps
CPU time 21 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:44:18 PM PDT 24
Peak memory 197208 kb
Host smart-bdf76798-7173-4422-b0ae-fdce67b560c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503161009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1503161009
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2446605871
Short name T1
Test name
Test status
Simulation time 113814296 ps
CPU time 0.67 seconds
Started Jul 19 04:43:27 PM PDT 24
Finished Jul 19 04:43:34 PM PDT 24
Peak memory 194876 kb
Host smart-88b0dd7d-c4f7-4270-88c9-41d0ff231802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446605871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2446605871
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1316527908
Short name T590
Test name
Test status
Simulation time 204218957 ps
CPU time 0.77 seconds
Started Jul 19 04:43:33 PM PDT 24
Finished Jul 19 04:43:41 PM PDT 24
Peak memory 196320 kb
Host smart-5a2722b0-9e84-433c-aa70-e2ba1629e81d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316527908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1316527908
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4271714793
Short name T667
Test name
Test status
Simulation time 87669665 ps
CPU time 3.55 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:39 PM PDT 24
Peak memory 198248 kb
Host smart-9dc8e830-0e12-4d64-914b-8fc1839f9392
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271714793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4271714793
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3818696960
Short name T531
Test name
Test status
Simulation time 113790269 ps
CPU time 2.28 seconds
Started Jul 19 04:43:27 PM PDT 24
Finished Jul 19 04:43:36 PM PDT 24
Peak memory 196752 kb
Host smart-e88dbd58-df93-42e9-8ed0-db1ac7e476bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818696960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3818696960
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4101178184
Short name T541
Test name
Test status
Simulation time 51418649 ps
CPU time 1.03 seconds
Started Jul 19 04:43:34 PM PDT 24
Finished Jul 19 04:43:42 PM PDT 24
Peak memory 196940 kb
Host smart-3ee1efb3-bc2d-4280-8c93-060d9feb331c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101178184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4101178184
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2831298051
Short name T462
Test name
Test status
Simulation time 172578305 ps
CPU time 0.72 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 195608 kb
Host smart-79189113-9682-41b0-8bc5-b3bdc17e947f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831298051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2831298051
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2664245250
Short name T550
Test name
Test status
Simulation time 437641615 ps
CPU time 5.71 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 198320 kb
Host smart-6b70afd1-2d79-4ad0-b28f-47e03ffb1b61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664245250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2664245250
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.93569192
Short name T248
Test name
Test status
Simulation time 315844057 ps
CPU time 1.32 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:36 PM PDT 24
Peak memory 195980 kb
Host smart-2a1b73b0-589b-4536-8909-8207c131328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93569192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.93569192
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.4115498961
Short name T189
Test name
Test status
Simulation time 57007322 ps
CPU time 1.11 seconds
Started Jul 19 04:43:35 PM PDT 24
Finished Jul 19 04:43:43 PM PDT 24
Peak memory 196640 kb
Host smart-b56bbd02-ed7c-45cd-adbd-006ff201a13e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115498961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.4115498961
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3427278135
Short name T546
Test name
Test status
Simulation time 20138985432 ps
CPU time 84.73 seconds
Started Jul 19 04:43:32 PM PDT 24
Finished Jul 19 04:45:04 PM PDT 24
Peak memory 198288 kb
Host smart-51bf59a7-07e0-438d-b59e-cda4ba4dffdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427278135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3427278135
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3451726204
Short name T578
Test name
Test status
Simulation time 24177390 ps
CPU time 0.56 seconds
Started Jul 19 04:43:54 PM PDT 24
Finished Jul 19 04:43:59 PM PDT 24
Peak memory 194420 kb
Host smart-14600531-ad57-4d9b-af29-f2c3969d2033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451726204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3451726204
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2396748380
Short name T410
Test name
Test status
Simulation time 60948459 ps
CPU time 0.74 seconds
Started Jul 19 04:43:35 PM PDT 24
Finished Jul 19 04:43:43 PM PDT 24
Peak memory 195404 kb
Host smart-bb6f00bd-0026-4b9f-a239-372b2ac76297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396748380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2396748380
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2563569033
Short name T405
Test name
Test status
Simulation time 854243624 ps
CPU time 22.98 seconds
Started Jul 19 04:43:47 PM PDT 24
Finished Jul 19 04:44:15 PM PDT 24
Peak memory 198236 kb
Host smart-61ffccb6-a9e0-4e71-bc81-aded72313f44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563569033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2563569033
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3774085134
Short name T294
Test name
Test status
Simulation time 364026674 ps
CPU time 1 seconds
Started Jul 19 04:43:41 PM PDT 24
Finished Jul 19 04:43:48 PM PDT 24
Peak memory 198060 kb
Host smart-63140e96-8dc3-4a22-a08f-7a67fd8288dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774085134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3774085134
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.477822500
Short name T510
Test name
Test status
Simulation time 33697842 ps
CPU time 0.99 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:43:59 PM PDT 24
Peak memory 197020 kb
Host smart-21ef30b6-62c2-4075-96a6-eb9d0d089a86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477822500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.477822500
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2732760995
Short name T257
Test name
Test status
Simulation time 151704285 ps
CPU time 1.69 seconds
Started Jul 19 04:43:40 PM PDT 24
Finished Jul 19 04:43:48 PM PDT 24
Peak memory 197036 kb
Host smart-f9e513ac-7612-4d44-ac2a-1125b5c0d5e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732760995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2732760995
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.226020694
Short name T413
Test name
Test status
Simulation time 466828719 ps
CPU time 1.55 seconds
Started Jul 19 04:43:46 PM PDT 24
Finished Jul 19 04:43:53 PM PDT 24
Peak memory 196300 kb
Host smart-bd4391bc-ae03-4794-a5d3-842f0ff55cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226020694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
226020694
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2478855176
Short name T520
Test name
Test status
Simulation time 61132208 ps
CPU time 1.28 seconds
Started Jul 19 04:43:42 PM PDT 24
Finished Jul 19 04:43:49 PM PDT 24
Peak memory 197124 kb
Host smart-9da22dee-aa07-47cd-ad7d-a7b2fa41c8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478855176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2478855176
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.855791745
Short name T124
Test name
Test status
Simulation time 32720312 ps
CPU time 1.21 seconds
Started Jul 19 04:43:39 PM PDT 24
Finished Jul 19 04:43:46 PM PDT 24
Peak memory 198204 kb
Host smart-013acd48-f635-4839-a622-e73c4e83b5d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855791745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.855791745
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2643938342
Short name T618
Test name
Test status
Simulation time 1408101463 ps
CPU time 1.33 seconds
Started Jul 19 04:43:48 PM PDT 24
Finished Jul 19 04:43:54 PM PDT 24
Peak memory 198124 kb
Host smart-2a809073-0734-49e0-a574-c147d5c82e75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643938342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2643938342
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2329368895
Short name T209
Test name
Test status
Simulation time 32237958 ps
CPU time 0.83 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 196104 kb
Host smart-c9718f3a-03e2-473b-9cce-1ed14c3427b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329368895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2329368895
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3694910142
Short name T132
Test name
Test status
Simulation time 191414415 ps
CPU time 1.46 seconds
Started Jul 19 04:43:37 PM PDT 24
Finished Jul 19 04:43:45 PM PDT 24
Peak memory 197068 kb
Host smart-d7e2eb12-771d-41da-9270-50f4abf56c9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694910142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3694910142
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1131567153
Short name T672
Test name
Test status
Simulation time 58174761 ps
CPU time 0.56 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:08 PM PDT 24
Peak memory 194200 kb
Host smart-52d179f9-2b93-4fe3-b9e8-601e31862095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131567153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1131567153
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.448196839
Short name T640
Test name
Test status
Simulation time 61155565 ps
CPU time 0.92 seconds
Started Jul 19 04:43:41 PM PDT 24
Finished Jul 19 04:43:48 PM PDT 24
Peak memory 195948 kb
Host smart-b22de16c-e735-4533-ac43-8334b9cd2d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448196839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.448196839
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.703394565
Short name T679
Test name
Test status
Simulation time 1193570484 ps
CPU time 25.76 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:25 PM PDT 24
Peak memory 195700 kb
Host smart-26e42ed5-726c-48ce-8829-42966c7c56e0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703394565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.703394565
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1048203610
Short name T498
Test name
Test status
Simulation time 410004617 ps
CPU time 1.04 seconds
Started Jul 19 04:43:46 PM PDT 24
Finished Jul 19 04:43:53 PM PDT 24
Peak memory 198208 kb
Host smart-c41d7b6b-0ed7-4b21-93fa-afb033af5d13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048203610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1048203610
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.799874269
Short name T230
Test name
Test status
Simulation time 77469337 ps
CPU time 1.32 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:08 PM PDT 24
Peak memory 196012 kb
Host smart-affe72cb-41b9-43df-be6e-537fca3e966b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799874269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.799874269
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3049784301
Short name T227
Test name
Test status
Simulation time 435266080 ps
CPU time 3.45 seconds
Started Jul 19 04:43:43 PM PDT 24
Finished Jul 19 04:43:52 PM PDT 24
Peak memory 198300 kb
Host smart-203a127b-289b-4456-b864-288d3dce9e69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049784301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3049784301
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1195259242
Short name T587
Test name
Test status
Simulation time 194904210 ps
CPU time 1.03 seconds
Started Jul 19 04:43:37 PM PDT 24
Finished Jul 19 04:43:44 PM PDT 24
Peak memory 196632 kb
Host smart-6d98a39d-4f7b-43a4-9d43-28228e4af6e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195259242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1195259242
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2724504086
Short name T635
Test name
Test status
Simulation time 143871927 ps
CPU time 0.85 seconds
Started Jul 19 04:43:48 PM PDT 24
Finished Jul 19 04:43:53 PM PDT 24
Peak memory 196444 kb
Host smart-01bc1cf5-d8e0-4100-9527-3f3a4650bd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724504086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2724504086
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.845142609
Short name T709
Test name
Test status
Simulation time 92840264 ps
CPU time 1 seconds
Started Jul 19 04:43:42 PM PDT 24
Finished Jul 19 04:43:49 PM PDT 24
Peak memory 196208 kb
Host smart-61a5e0e5-b91d-4931-bbfe-eb186bf4d212
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845142609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.845142609
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2717721274
Short name T391
Test name
Test status
Simulation time 83645290 ps
CPU time 3.63 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 04:44:07 PM PDT 24
Peak memory 198196 kb
Host smart-5623e470-c1d7-4e41-84fb-551fdc624a61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717721274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2717721274
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3697208613
Short name T375
Test name
Test status
Simulation time 141294084 ps
CPU time 1.16 seconds
Started Jul 19 04:43:45 PM PDT 24
Finished Jul 19 04:43:52 PM PDT 24
Peak memory 196076 kb
Host smart-84fd34ec-5f3d-4102-99a4-ec3c9b0680f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697208613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3697208613
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2147103988
Short name T392
Test name
Test status
Simulation time 143033744 ps
CPU time 1.13 seconds
Started Jul 19 04:43:38 PM PDT 24
Finished Jul 19 04:43:45 PM PDT 24
Peak memory 196068 kb
Host smart-711d5a71-11fa-49e9-a41e-854fe517219f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147103988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2147103988
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2221136589
Short name T174
Test name
Test status
Simulation time 6146148512 ps
CPU time 83.02 seconds
Started Jul 19 04:43:33 PM PDT 24
Finished Jul 19 04:45:04 PM PDT 24
Peak memory 198384 kb
Host smart-695ed601-055a-4943-a480-1cf8cf33c914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221136589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2221136589
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.311089221
Short name T36
Test name
Test status
Simulation time 670164195363 ps
CPU time 680.11 seconds
Started Jul 19 04:43:46 PM PDT 24
Finished Jul 19 04:55:12 PM PDT 24
Peak memory 198364 kb
Host smart-07165119-5cbf-4717-8f92-05c7541540c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=311089221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.311089221
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1812044654
Short name T244
Test name
Test status
Simulation time 22716412 ps
CPU time 0.58 seconds
Started Jul 19 04:43:43 PM PDT 24
Finished Jul 19 04:43:50 PM PDT 24
Peak memory 194884 kb
Host smart-f6b335af-b6da-4588-a935-ec443884202a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812044654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1812044654
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3784863779
Short name T26
Test name
Test status
Simulation time 83062087 ps
CPU time 0.86 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:13 PM PDT 24
Peak memory 196704 kb
Host smart-e91fb3fa-5447-4b34-a9de-4d995cfa42eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784863779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3784863779
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1874181996
Short name T369
Test name
Test status
Simulation time 781940249 ps
CPU time 8.83 seconds
Started Jul 19 04:43:58 PM PDT 24
Finished Jul 19 04:44:12 PM PDT 24
Peak memory 197148 kb
Host smart-9b81c98c-2573-4bb8-b250-4d25adcf7fd3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874181996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1874181996
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2015071601
Short name T31
Test name
Test status
Simulation time 263508424 ps
CPU time 0.96 seconds
Started Jul 19 04:43:39 PM PDT 24
Finished Jul 19 04:43:46 PM PDT 24
Peak memory 197316 kb
Host smart-cc99199f-1ecc-4621-97bf-3917ad77c69d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015071601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2015071601
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3523030233
Short name T191
Test name
Test status
Simulation time 119054880 ps
CPU time 0.93 seconds
Started Jul 19 04:43:51 PM PDT 24
Finished Jul 19 04:43:55 PM PDT 24
Peak memory 196056 kb
Host smart-219619f6-4ba5-4e14-bb14-a36235da45b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523030233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3523030233
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2503792154
Short name T595
Test name
Test status
Simulation time 37394432 ps
CPU time 1.54 seconds
Started Jul 19 04:43:48 PM PDT 24
Finished Jul 19 04:43:54 PM PDT 24
Peak memory 196892 kb
Host smart-ea3b45d4-92a4-49fe-90b6-95ef3dc939d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503792154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2503792154
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1235717383
Short name T120
Test name
Test status
Simulation time 84189424 ps
CPU time 1.42 seconds
Started Jul 19 04:43:43 PM PDT 24
Finished Jul 19 04:43:51 PM PDT 24
Peak memory 196328 kb
Host smart-0451b28e-d5d5-4a83-9837-10a21b05fae7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235717383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1235717383
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.552891075
Short name T312
Test name
Test status
Simulation time 49276532 ps
CPU time 0.77 seconds
Started Jul 19 04:43:38 PM PDT 24
Finished Jul 19 04:43:45 PM PDT 24
Peak memory 196264 kb
Host smart-b9ba4190-2e0b-4938-9e5d-0f94247bfdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552891075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.552891075
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1404650804
Short name T24
Test name
Test status
Simulation time 41776640 ps
CPU time 0.65 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 04:44:07 PM PDT 24
Peak memory 195184 kb
Host smart-1e352397-fc3d-4f05-a974-3e1799e7158f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404650804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1404650804
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3114116070
Short name T95
Test name
Test status
Simulation time 471073787 ps
CPU time 4.52 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 198164 kb
Host smart-547f4ed6-effa-48e0-b196-da20384d9be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114116070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3114116070
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2936549532
Short name T60
Test name
Test status
Simulation time 64111195 ps
CPU time 0.96 seconds
Started Jul 19 04:43:42 PM PDT 24
Finished Jul 19 04:43:49 PM PDT 24
Peak memory 195928 kb
Host smart-6a28c01a-0d3c-445c-8e27-bf409dff3cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936549532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2936549532
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1271318345
Short name T446
Test name
Test status
Simulation time 336914136 ps
CPU time 1.33 seconds
Started Jul 19 04:43:47 PM PDT 24
Finished Jul 19 04:43:54 PM PDT 24
Peak memory 196912 kb
Host smart-0d2a69db-88f0-42fb-adfa-5e7ae829a584
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271318345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1271318345
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.90333696
Short name T393
Test name
Test status
Simulation time 4757945998 ps
CPU time 51.67 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 04:44:54 PM PDT 24
Peak memory 198284 kb
Host smart-94906720-fafb-48a0-b02e-c308993b3be0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90333696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gp
io_stress_all.90333696
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.242123234
Short name T562
Test name
Test status
Simulation time 39334164 ps
CPU time 0.54 seconds
Started Jul 19 04:43:46 PM PDT 24
Finished Jul 19 04:43:52 PM PDT 24
Peak memory 194120 kb
Host smart-90d73e33-ee56-4e28-af7b-792829dab5d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242123234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.242123234
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1910305097
Short name T323
Test name
Test status
Simulation time 14768117 ps
CPU time 0.6 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 04:44:06 PM PDT 24
Peak memory 194952 kb
Host smart-454768f6-e800-4db5-9c52-946067331b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910305097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1910305097
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.170380128
Short name T361
Test name
Test status
Simulation time 420066496 ps
CPU time 20.82 seconds
Started Jul 19 04:44:03 PM PDT 24
Finished Jul 19 04:44:30 PM PDT 24
Peak memory 198160 kb
Host smart-4c20da2a-c6bb-436c-81c5-619f6cbaf9d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170380128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.170380128
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.975218596
Short name T665
Test name
Test status
Simulation time 271801607 ps
CPU time 1.05 seconds
Started Jul 19 04:43:43 PM PDT 24
Finished Jul 19 04:43:50 PM PDT 24
Peak memory 196820 kb
Host smart-ee5d7253-4b9b-44aa-b61a-7df3284f5c9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975218596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.975218596
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.35559886
Short name T70
Test name
Test status
Simulation time 50972640 ps
CPU time 0.76 seconds
Started Jul 19 04:44:07 PM PDT 24
Finished Jul 19 04:44:15 PM PDT 24
Peak memory 195644 kb
Host smart-740e3cd7-9619-4e54-98ea-a6530e306311
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35559886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.35559886
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3185933679
Short name T482
Test name
Test status
Simulation time 1476732584 ps
CPU time 2.83 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 198284 kb
Host smart-9d0ec924-72db-45b4-a6bc-8a692dcc9a48
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185933679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3185933679
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3054568235
Short name T430
Test name
Test status
Simulation time 32442177 ps
CPU time 0.86 seconds
Started Jul 19 04:44:03 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 194708 kb
Host smart-0ea19052-5349-4ecf-b1fb-7eacd2a929ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054568235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3054568235
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1598390690
Short name T137
Test name
Test status
Simulation time 148701479 ps
CPU time 0.99 seconds
Started Jul 19 04:43:52 PM PDT 24
Finished Jul 19 04:43:57 PM PDT 24
Peak memory 196872 kb
Host smart-0dfd3182-a515-4459-a5ae-efc19eadaeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598390690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1598390690
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2083433154
Short name T556
Test name
Test status
Simulation time 94247499 ps
CPU time 1.02 seconds
Started Jul 19 04:43:40 PM PDT 24
Finished Jul 19 04:43:47 PM PDT 24
Peak memory 196012 kb
Host smart-504f652b-490a-4a6d-b205-9e5553946c2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083433154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2083433154
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3809108262
Short name T553
Test name
Test status
Simulation time 1546949746 ps
CPU time 3.69 seconds
Started Jul 19 04:43:41 PM PDT 24
Finished Jul 19 04:43:51 PM PDT 24
Peak memory 198168 kb
Host smart-ba9f18f8-87ff-4176-b886-34b48a32ef24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809108262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3809108262
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1563050552
Short name T229
Test name
Test status
Simulation time 44773842 ps
CPU time 0.97 seconds
Started Jul 19 04:43:39 PM PDT 24
Finished Jul 19 04:43:46 PM PDT 24
Peak memory 197360 kb
Host smart-a59b58a6-6a48-4474-a818-39fdb87b70bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563050552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1563050552
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.468309668
Short name T407
Test name
Test status
Simulation time 91756676 ps
CPU time 1.27 seconds
Started Jul 19 04:43:47 PM PDT 24
Finished Jul 19 04:43:54 PM PDT 24
Peak memory 195756 kb
Host smart-71219027-4b57-4107-af95-539408fe55b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468309668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.468309668
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2411574538
Short name T165
Test name
Test status
Simulation time 4773539288 ps
CPU time 124.53 seconds
Started Jul 19 04:43:59 PM PDT 24
Finished Jul 19 04:46:09 PM PDT 24
Peak memory 198252 kb
Host smart-1a70ca5d-0e39-497e-b168-d30e6915690d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411574538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2411574538
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2274558308
Short name T383
Test name
Test status
Simulation time 178350939 ps
CPU time 0.55 seconds
Started Jul 19 04:43:40 PM PDT 24
Finished Jul 19 04:43:46 PM PDT 24
Peak memory 194120 kb
Host smart-a27b11c0-5189-4bd1-9ae7-be05183f81b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274558308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2274558308
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3147706017
Short name T141
Test name
Test status
Simulation time 186548204 ps
CPU time 0.87 seconds
Started Jul 19 04:43:46 PM PDT 24
Finished Jul 19 04:43:52 PM PDT 24
Peak memory 196636 kb
Host smart-d61e9018-3780-4c48-a23c-137beec84989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147706017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3147706017
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2414859052
Short name T654
Test name
Test status
Simulation time 1388515438 ps
CPU time 17.57 seconds
Started Jul 19 04:43:41 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 195868 kb
Host smart-1f21aada-ed57-4e30-a4c0-61462fe08c52
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414859052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2414859052
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3476259636
Short name T335
Test name
Test status
Simulation time 124028959 ps
CPU time 0.91 seconds
Started Jul 19 04:43:48 PM PDT 24
Finished Jul 19 04:43:53 PM PDT 24
Peak memory 196236 kb
Host smart-2fbad1be-e8eb-47ab-8263-70aa1090fc99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476259636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3476259636
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1121499827
Short name T153
Test name
Test status
Simulation time 29620460 ps
CPU time 0.76 seconds
Started Jul 19 04:43:42 PM PDT 24
Finished Jul 19 04:43:49 PM PDT 24
Peak memory 195652 kb
Host smart-bd7ca533-f978-4baa-9428-1c28e7f73b18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121499827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1121499827
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2621948875
Short name T176
Test name
Test status
Simulation time 96972745 ps
CPU time 1.16 seconds
Started Jul 19 04:43:37 PM PDT 24
Finished Jul 19 04:43:44 PM PDT 24
Peak memory 198100 kb
Host smart-f6418b26-d636-41d2-bb88-0fce64947860
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621948875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2621948875
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.963289135
Short name T652
Test name
Test status
Simulation time 101193815 ps
CPU time 1.97 seconds
Started Jul 19 04:43:41 PM PDT 24
Finished Jul 19 04:43:49 PM PDT 24
Peak memory 196040 kb
Host smart-ead84278-4120-4aa2-8559-8f5205f9eb62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963289135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
963289135
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.665892921
Short name T445
Test name
Test status
Simulation time 70019672 ps
CPU time 1.39 seconds
Started Jul 19 04:43:40 PM PDT 24
Finished Jul 19 04:43:47 PM PDT 24
Peak memory 198260 kb
Host smart-60d8e555-8d49-424b-a734-91f67121366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665892921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.665892921
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2152857852
Short name T452
Test name
Test status
Simulation time 39904668 ps
CPU time 0.96 seconds
Started Jul 19 04:43:45 PM PDT 24
Finished Jul 19 04:43:52 PM PDT 24
Peak memory 195936 kb
Host smart-a29e7d59-6672-4e04-9412-4506c4e913f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152857852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2152857852
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.945695696
Short name T280
Test name
Test status
Simulation time 148000333 ps
CPU time 3.38 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:12 PM PDT 24
Peak memory 198216 kb
Host smart-9f3d783a-c3fc-4aa9-b5d1-c5f90379ab83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945695696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.945695696
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.4226398094
Short name T555
Test name
Test status
Simulation time 66121944 ps
CPU time 0.86 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 196236 kb
Host smart-0cfca49c-f091-466f-87c6-780a8b779a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226398094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.4226398094
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.217614441
Short name T525
Test name
Test status
Simulation time 161507281 ps
CPU time 0.85 seconds
Started Jul 19 04:43:59 PM PDT 24
Finished Jul 19 04:44:06 PM PDT 24
Peak memory 195420 kb
Host smart-007d36a8-557a-4dd7-8f71-8e154972fa23
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217614441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.217614441
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.71354428
Short name T259
Test name
Test status
Simulation time 18992920366 ps
CPU time 55.74 seconds
Started Jul 19 04:43:41 PM PDT 24
Finished Jul 19 04:44:43 PM PDT 24
Peak memory 198344 kb
Host smart-8db14aa4-29d1-476d-bbc5-9abe14f3cf6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71354428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gp
io_stress_all.71354428
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.905596583
Short name T561
Test name
Test status
Simulation time 15927964 ps
CPU time 0.58 seconds
Started Jul 19 04:43:45 PM PDT 24
Finished Jul 19 04:43:51 PM PDT 24
Peak memory 195060 kb
Host smart-6aa678fe-12c4-431c-89ec-b76b71e310c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905596583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.905596583
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.468737449
Short name T657
Test name
Test status
Simulation time 34724580 ps
CPU time 0.79 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:13 PM PDT 24
Peak memory 195480 kb
Host smart-a0c15d77-707b-48f9-955e-48bc2bb50903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468737449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.468737449
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4101659665
Short name T537
Test name
Test status
Simulation time 478700538 ps
CPU time 13.34 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 04:44:16 PM PDT 24
Peak memory 197084 kb
Host smart-816c75b0-2ec2-4b8c-8950-ee37dc1257cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101659665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4101659665
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1194158040
Short name T402
Test name
Test status
Simulation time 77311567 ps
CPU time 0.98 seconds
Started Jul 19 04:43:47 PM PDT 24
Finished Jul 19 04:43:53 PM PDT 24
Peak memory 196788 kb
Host smart-94c1c2fa-edb6-4399-9bb0-5352d5a6be69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194158040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1194158040
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2687123711
Short name T542
Test name
Test status
Simulation time 197063775 ps
CPU time 0.98 seconds
Started Jul 19 04:44:08 PM PDT 24
Finished Jul 19 04:44:16 PM PDT 24
Peak memory 196720 kb
Host smart-c4c1faf7-0d21-4955-ba00-10cddde0a2aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687123711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2687123711
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2625044908
Short name T206
Test name
Test status
Simulation time 493995061 ps
CPU time 1.9 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 198200 kb
Host smart-14d78d3b-4bc9-407b-889d-71183912c8ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625044908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2625044908
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1635471715
Short name T73
Test name
Test status
Simulation time 125054748 ps
CPU time 3.51 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:44:01 PM PDT 24
Peak memory 198284 kb
Host smart-c402385a-ce6c-44c3-acf1-c8d10f318c3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635471715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1635471715
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2043198978
Short name T689
Test name
Test status
Simulation time 33106879 ps
CPU time 1.05 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:13 PM PDT 24
Peak memory 196244 kb
Host smart-e77c40d6-3243-4d93-b759-738044af5ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043198978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2043198978
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.698957912
Short name T420
Test name
Test status
Simulation time 19368396 ps
CPU time 0.66 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 04:44:07 PM PDT 24
Peak memory 194452 kb
Host smart-bf56cb0f-6733-4a7b-9d06-9b81a603c1a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698957912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.698957912
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.293592437
Short name T289
Test name
Test status
Simulation time 72288391 ps
CPU time 1.48 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:01 PM PDT 24
Peak memory 198144 kb
Host smart-bbdc1561-89de-466d-8614-cb872a739cb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293592437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.293592437
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.157119564
Short name T376
Test name
Test status
Simulation time 63067565 ps
CPU time 1.23 seconds
Started Jul 19 04:43:47 PM PDT 24
Finished Jul 19 04:43:53 PM PDT 24
Peak memory 196468 kb
Host smart-47a38206-89d9-49b4-90a9-77d19fe3293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157119564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.157119564
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2548905509
Short name T119
Test name
Test status
Simulation time 45338409 ps
CPU time 1.19 seconds
Started Jul 19 04:43:38 PM PDT 24
Finished Jul 19 04:43:45 PM PDT 24
Peak memory 195756 kb
Host smart-0441c783-6d31-47a0-a828-70bb379c3126
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548905509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2548905509
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.520256530
Short name T341
Test name
Test status
Simulation time 4950994667 ps
CPU time 67.58 seconds
Started Jul 19 04:43:49 PM PDT 24
Finished Jul 19 04:45:00 PM PDT 24
Peak memory 198208 kb
Host smart-61dee7ef-e7ba-467e-a37a-d8f104367203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520256530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.520256530
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3294872526
Short name T65
Test name
Test status
Simulation time 256309015886 ps
CPU time 1747.42 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 05:13:10 PM PDT 24
Peak memory 198436 kb
Host smart-9345c383-7857-470c-8edd-7ba4c29a07ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3294872526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3294872526
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.411583232
Short name T243
Test name
Test status
Simulation time 18371255 ps
CPU time 0.57 seconds
Started Jul 19 04:43:51 PM PDT 24
Finished Jul 19 04:43:56 PM PDT 24
Peak memory 195108 kb
Host smart-92abb118-13b3-4585-a299-e994a4cc3b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411583232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.411583232
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3287095779
Short name T372
Test name
Test status
Simulation time 27295945 ps
CPU time 0.66 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 195000 kb
Host smart-259e5b68-9de5-46b2-8aae-851936eb9c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287095779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3287095779
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3979432910
Short name T381
Test name
Test status
Simulation time 274174448 ps
CPU time 7.48 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 197044 kb
Host smart-a660f3e9-20f7-40d3-b54c-ba18face7646
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979432910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3979432910
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.4057886000
Short name T216
Test name
Test status
Simulation time 84014861 ps
CPU time 0.6 seconds
Started Jul 19 04:43:42 PM PDT 24
Finished Jul 19 04:43:49 PM PDT 24
Peak memory 194592 kb
Host smart-570de3a4-84a5-425c-ab46-fdafa671a64a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057886000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.4057886000
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2956313669
Short name T557
Test name
Test status
Simulation time 67465992 ps
CPU time 1.05 seconds
Started Jul 19 04:43:50 PM PDT 24
Finished Jul 19 04:43:54 PM PDT 24
Peak memory 196176 kb
Host smart-afa65ff6-7197-44f9-8121-b170cfbecc34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956313669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2956313669
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.4292150031
Short name T225
Test name
Test status
Simulation time 30942125 ps
CPU time 1.27 seconds
Started Jul 19 04:43:50 PM PDT 24
Finished Jul 19 04:43:55 PM PDT 24
Peak memory 195356 kb
Host smart-5f3fcc9f-6654-43db-8101-37c9898dba50
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292150031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.4292150031
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2406140289
Short name T477
Test name
Test status
Simulation time 213330819 ps
CPU time 2.39 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 04:44:09 PM PDT 24
Peak memory 197348 kb
Host smart-70c97207-d86b-4f26-923f-f0e211746848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406140289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2406140289
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2602854432
Short name T279
Test name
Test status
Simulation time 71388566 ps
CPU time 0.7 seconds
Started Jul 19 04:44:03 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 195180 kb
Host smart-59eb7f04-d4a6-425b-921c-1e9892270b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602854432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2602854432
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2416383552
Short name T183
Test name
Test status
Simulation time 75521540 ps
CPU time 1.2 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 196048 kb
Host smart-6f747e13-c90f-4c24-930b-3a215b2c1d6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416383552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2416383552
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3961847704
Short name T345
Test name
Test status
Simulation time 578243834 ps
CPU time 4.59 seconds
Started Jul 19 04:43:50 PM PDT 24
Finished Jul 19 04:43:58 PM PDT 24
Peak memory 196968 kb
Host smart-658c6798-0022-41bb-a66f-79c060062427
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961847704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3961847704
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3919743895
Short name T506
Test name
Test status
Simulation time 319640734 ps
CPU time 1.38 seconds
Started Jul 19 04:43:50 PM PDT 24
Finished Jul 19 04:43:55 PM PDT 24
Peak memory 198228 kb
Host smart-1ba122e7-7bf0-4186-942d-bceef6188a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919743895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3919743895
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3780595375
Short name T457
Test name
Test status
Simulation time 45767190 ps
CPU time 1.31 seconds
Started Jul 19 04:44:12 PM PDT 24
Finished Jul 19 04:44:19 PM PDT 24
Peak memory 197040 kb
Host smart-3ea610af-abc7-4190-a141-a9425f124930
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780595375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3780595375
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1181834198
Short name T100
Test name
Test status
Simulation time 61060302379 ps
CPU time 194.2 seconds
Started Jul 19 04:43:52 PM PDT 24
Finished Jul 19 04:47:10 PM PDT 24
Peak memory 198308 kb
Host smart-2e59d2af-de3b-4f9a-8a5e-1cb19121894b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181834198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1181834198
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3394818181
Short name T417
Test name
Test status
Simulation time 16584147 ps
CPU time 0.56 seconds
Started Jul 19 04:43:44 PM PDT 24
Finished Jul 19 04:43:50 PM PDT 24
Peak memory 194144 kb
Host smart-56f8f06d-182e-4ebd-91cc-2f92f1ceb935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394818181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3394818181
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1147269643
Short name T606
Test name
Test status
Simulation time 95194713 ps
CPU time 0.87 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:43:58 PM PDT 24
Peak memory 196520 kb
Host smart-bcc67e1d-ff16-42ac-b0ef-6a1e9dbeeda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147269643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1147269643
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4057719841
Short name T486
Test name
Test status
Simulation time 874543040 ps
CPU time 14.32 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:21 PM PDT 24
Peak memory 196432 kb
Host smart-f9e08da3-544c-42bc-9f05-2d0b83180646
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057719841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4057719841
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1944793520
Short name T605
Test name
Test status
Simulation time 75532996 ps
CPU time 0.68 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:43:58 PM PDT 24
Peak memory 195588 kb
Host smart-a799e96a-35e4-49c9-b594-f4857740cef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944793520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1944793520
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3889636862
Short name T577
Test name
Test status
Simulation time 81131303 ps
CPU time 0.81 seconds
Started Jul 19 04:43:45 PM PDT 24
Finished Jul 19 04:43:51 PM PDT 24
Peak memory 195580 kb
Host smart-6fa2e4f5-2669-4603-8d2d-4f0c8e0444ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889636862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3889636862
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.731820893
Short name T80
Test name
Test status
Simulation time 264120346 ps
CPU time 1.96 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:44:00 PM PDT 24
Peak memory 196668 kb
Host smart-783cf2ec-16d4-4c9f-b645-e53430646f0c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731820893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.731820893
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3716537848
Short name T297
Test name
Test status
Simulation time 124221926 ps
CPU time 2.53 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:44:00 PM PDT 24
Peak memory 197104 kb
Host smart-317bb8f2-06bd-4266-adb3-741bbed89166
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716537848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3716537848
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1344112113
Short name T671
Test name
Test status
Simulation time 21421792 ps
CPU time 0.83 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:09 PM PDT 24
Peak memory 196588 kb
Host smart-32650770-ba3c-436b-8d9a-3175f2381d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344112113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1344112113
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3666041000
Short name T290
Test name
Test status
Simulation time 105282983 ps
CPU time 1.15 seconds
Started Jul 19 04:43:41 PM PDT 24
Finished Jul 19 04:43:48 PM PDT 24
Peak memory 197304 kb
Host smart-2d3bac5e-0ead-4b89-be4f-4ecd51d058ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666041000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3666041000
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2236014919
Short name T712
Test name
Test status
Simulation time 69673059 ps
CPU time 3.44 seconds
Started Jul 19 04:43:45 PM PDT 24
Finished Jul 19 04:43:55 PM PDT 24
Peak memory 198160 kb
Host smart-450c1bba-68bd-496c-a7ba-f8d4ffa06b60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236014919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2236014919
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1339132279
Short name T600
Test name
Test status
Simulation time 103656142 ps
CPU time 0.9 seconds
Started Jul 19 04:43:43 PM PDT 24
Finished Jul 19 04:43:50 PM PDT 24
Peak memory 196636 kb
Host smart-cc4c4e7b-d607-484b-a4aa-8aad26cab497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339132279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1339132279
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1258578467
Short name T152
Test name
Test status
Simulation time 120117261 ps
CPU time 0.81 seconds
Started Jul 19 04:43:52 PM PDT 24
Finished Jul 19 04:43:57 PM PDT 24
Peak memory 195496 kb
Host smart-481c3ab7-a462-4711-9d26-a5fec0b261e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258578467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1258578467
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2666415515
Short name T7
Test name
Test status
Simulation time 20636383044 ps
CPU time 117.78 seconds
Started Jul 19 04:43:48 PM PDT 24
Finished Jul 19 04:45:51 PM PDT 24
Peak memory 198348 kb
Host smart-73752c6e-be4a-4ec2-9c0e-a11c24673fa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666415515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2666415515
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3261971823
Short name T528
Test name
Test status
Simulation time 198663283662 ps
CPU time 815.37 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:57:38 PM PDT 24
Peak memory 198504 kb
Host smart-7a9d419f-ff09-402c-bcf5-4433d26fc6ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3261971823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3261971823
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.4141178363
Short name T548
Test name
Test status
Simulation time 11899041 ps
CPU time 0.6 seconds
Started Jul 19 04:43:14 PM PDT 24
Finished Jul 19 04:43:16 PM PDT 24
Peak memory 194420 kb
Host smart-fb59d928-fea5-40d8-9559-2a625fc5f7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141178363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4141178363
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3059106130
Short name T615
Test name
Test status
Simulation time 259237821 ps
CPU time 0.89 seconds
Started Jul 19 04:43:19 PM PDT 24
Finished Jul 19 04:43:23 PM PDT 24
Peak memory 196684 kb
Host smart-c6bb158b-480a-4e65-a131-e35d5e9bf288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059106130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3059106130
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2113353016
Short name T648
Test name
Test status
Simulation time 416585224 ps
CPU time 8.84 seconds
Started Jul 19 04:43:15 PM PDT 24
Finished Jul 19 04:43:25 PM PDT 24
Peak memory 196912 kb
Host smart-ca6f812d-902b-4406-a4f2-bdb828b8df05
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113353016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2113353016
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1817288699
Short name T348
Test name
Test status
Simulation time 68632252 ps
CPU time 0.81 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:31 PM PDT 24
Peak memory 196240 kb
Host smart-e9a740a8-75ca-42b5-a4f3-7b8b3e970d4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817288699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1817288699
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.968537142
Short name T691
Test name
Test status
Simulation time 214647743 ps
CPU time 0.93 seconds
Started Jul 19 04:43:20 PM PDT 24
Finished Jul 19 04:43:23 PM PDT 24
Peak memory 196424 kb
Host smart-858fbf2d-f0f9-4d01-bf9c-27edb293f958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968537142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.968537142
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3768096805
Short name T260
Test name
Test status
Simulation time 309707396 ps
CPU time 1.02 seconds
Started Jul 19 04:43:18 PM PDT 24
Finished Jul 19 04:43:21 PM PDT 24
Peak memory 196552 kb
Host smart-9bf64647-caa9-4a8e-9970-394078a4a11d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768096805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3768096805
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1764477214
Short name T180
Test name
Test status
Simulation time 117624110 ps
CPU time 1.28 seconds
Started Jul 19 04:43:19 PM PDT 24
Finished Jul 19 04:43:23 PM PDT 24
Peak memory 196928 kb
Host smart-0472b3ca-b4d6-47c3-88f5-987c5fd6544d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764477214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1764477214
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3828945369
Short name T202
Test name
Test status
Simulation time 191885622 ps
CPU time 1.06 seconds
Started Jul 19 04:43:19 PM PDT 24
Finished Jul 19 04:43:23 PM PDT 24
Peak memory 196196 kb
Host smart-208d12b5-36bd-4afc-92da-d3ea67b2209a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828945369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3828945369
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1612363737
Short name T138
Test name
Test status
Simulation time 50313548 ps
CPU time 0.73 seconds
Started Jul 19 04:43:25 PM PDT 24
Finished Jul 19 04:43:28 PM PDT 24
Peak memory 195456 kb
Host smart-978a8ccb-cd78-4676-acdc-aff06f397d5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612363737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1612363737
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1692270158
Short name T25
Test name
Test status
Simulation time 606462363 ps
CPU time 4.96 seconds
Started Jul 19 04:43:18 PM PDT 24
Finished Jul 19 04:43:26 PM PDT 24
Peak memory 198160 kb
Host smart-106bdf6a-7b89-420a-b702-e0973b6f3f60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692270158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1692270158
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.926384045
Short name T40
Test name
Test status
Simulation time 610893240 ps
CPU time 0.96 seconds
Started Jul 19 04:43:25 PM PDT 24
Finished Jul 19 04:43:29 PM PDT 24
Peak memory 215344 kb
Host smart-7db9e6e8-b44f-4740-86b8-d087536be6f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926384045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.926384045
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1367221154
Short name T150
Test name
Test status
Simulation time 80106000 ps
CPU time 0.87 seconds
Started Jul 19 04:43:13 PM PDT 24
Finished Jul 19 04:43:15 PM PDT 24
Peak memory 195576 kb
Host smart-82a006b7-9abe-4a95-a38f-62e2b40f5f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367221154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1367221154
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1001175260
Short name T232
Test name
Test status
Simulation time 39705376 ps
CPU time 1.08 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:35 PM PDT 24
Peak memory 195936 kb
Host smart-3f6565d5-e4d6-40bb-b97c-3fc6e8051d56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001175260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1001175260
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3208881827
Short name T10
Test name
Test status
Simulation time 18862336176 ps
CPU time 47.82 seconds
Started Jul 19 04:43:24 PM PDT 24
Finished Jul 19 04:44:14 PM PDT 24
Peak memory 198348 kb
Host smart-e7cb3739-f42f-416c-9080-84c0d9e39340
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208881827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3208881827
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2835311221
Short name T151
Test name
Test status
Simulation time 33145061 ps
CPU time 0.57 seconds
Started Jul 19 04:43:54 PM PDT 24
Finished Jul 19 04:43:59 PM PDT 24
Peak memory 194836 kb
Host smart-d0054cc3-178c-4493-895d-d6529abcdad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835311221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2835311221
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1680027261
Short name T164
Test name
Test status
Simulation time 32465243 ps
CPU time 0.66 seconds
Started Jul 19 04:43:43 PM PDT 24
Finished Jul 19 04:43:50 PM PDT 24
Peak memory 194148 kb
Host smart-422dcfcc-9e3d-4485-a8c2-eee7a624ceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680027261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1680027261
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.864064087
Short name T585
Test name
Test status
Simulation time 2871676547 ps
CPU time 20.9 seconds
Started Jul 19 04:43:47 PM PDT 24
Finished Jul 19 04:44:13 PM PDT 24
Peak memory 196732 kb
Host smart-3374c31f-6470-4cb8-b7a2-86430fed76fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864064087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.864064087
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3192326225
Short name T172
Test name
Test status
Simulation time 111982477 ps
CPU time 0.91 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 195904 kb
Host smart-435f0aca-1711-43d7-ba02-5cf9eaefe12d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192326225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3192326225
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1177160563
Short name T403
Test name
Test status
Simulation time 86012443 ps
CPU time 1.12 seconds
Started Jul 19 04:43:58 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 196136 kb
Host smart-790d3d77-4e50-4480-a5be-c8c1b4a43b6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177160563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1177160563
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3435244747
Short name T438
Test name
Test status
Simulation time 122630157 ps
CPU time 2.3 seconds
Started Jul 19 04:44:06 PM PDT 24
Finished Jul 19 04:44:15 PM PDT 24
Peak memory 198064 kb
Host smart-a17ee10d-a75f-42d4-8d98-6d518d9b0801
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435244747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3435244747
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2015351647
Short name T580
Test name
Test status
Simulation time 42423065 ps
CPU time 1.34 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 196376 kb
Host smart-342f7f12-411a-412f-8821-c655a2c7b4b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015351647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2015351647
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1931033847
Short name T538
Test name
Test status
Simulation time 562410844 ps
CPU time 1.27 seconds
Started Jul 19 04:43:52 PM PDT 24
Finished Jul 19 04:43:57 PM PDT 24
Peak memory 196080 kb
Host smart-b5fa2bf5-8d72-41df-9b8f-657c727fe4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931033847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1931033847
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2976423803
Short name T435
Test name
Test status
Simulation time 61701198 ps
CPU time 1.18 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 04:44:07 PM PDT 24
Peak memory 198236 kb
Host smart-9780a242-8e86-4e8f-8449-ad3f90de3a0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976423803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2976423803
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2101168386
Short name T683
Test name
Test status
Simulation time 1173440056 ps
CPU time 4.36 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:12 PM PDT 24
Peak memory 198156 kb
Host smart-c2d54604-e531-4b79-a55c-b56d1ce7d0e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101168386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2101168386
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2207045652
Short name T226
Test name
Test status
Simulation time 73013529 ps
CPU time 1.1 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:43:59 PM PDT 24
Peak memory 195752 kb
Host smart-b84d90b2-ffe2-4919-ae1d-0df3d194b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207045652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2207045652
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3371826801
Short name T211
Test name
Test status
Simulation time 227636544 ps
CPU time 0.89 seconds
Started Jul 19 04:43:39 PM PDT 24
Finished Jul 19 04:43:45 PM PDT 24
Peak memory 195444 kb
Host smart-94d1c04d-69d9-4ee5-af00-55f6dcbd41bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371826801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3371826801
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2306121168
Short name T235
Test name
Test status
Simulation time 23956375257 ps
CPU time 151.78 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:46:32 PM PDT 24
Peak memory 198320 kb
Host smart-fbca166d-877e-4ed3-acab-484945837a18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306121168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2306121168
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3853951588
Short name T63
Test name
Test status
Simulation time 99414980162 ps
CPU time 1519.64 seconds
Started Jul 19 04:43:54 PM PDT 24
Finished Jul 19 05:09:18 PM PDT 24
Peak memory 198456 kb
Host smart-64ae13bd-99d3-484b-be1b-f357d8fbc79f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3853951588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.3853951588
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1470594153
Short name T649
Test name
Test status
Simulation time 91128089 ps
CPU time 0.64 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 194148 kb
Host smart-78c501d5-17a4-4db7-a766-5de918d0e478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470594153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1470594153
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2873489607
Short name T192
Test name
Test status
Simulation time 155040414 ps
CPU time 0.7 seconds
Started Jul 19 04:44:14 PM PDT 24
Finished Jul 19 04:44:21 PM PDT 24
Peak memory 194332 kb
Host smart-3b237e92-7d0e-4b92-bb36-e6991bebed5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873489607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2873489607
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4069318484
Short name T638
Test name
Test status
Simulation time 464407304 ps
CPU time 12.56 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 04:44:15 PM PDT 24
Peak memory 197136 kb
Host smart-79576c9d-e15f-4329-ba62-737be638f668
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069318484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4069318484
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.735351070
Short name T396
Test name
Test status
Simulation time 59162727 ps
CPU time 0.68 seconds
Started Jul 19 04:44:08 PM PDT 24
Finished Jul 19 04:44:16 PM PDT 24
Peak memory 194660 kb
Host smart-d53ea723-615f-41d7-890c-b7bc0f5edc2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735351070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.735351070
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1966773744
Short name T388
Test name
Test status
Simulation time 256610018 ps
CPU time 1.01 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:00 PM PDT 24
Peak memory 196436 kb
Host smart-7c139393-04a2-4f80-a529-52a16aca9383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966773744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1966773744
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1893481940
Short name T473
Test name
Test status
Simulation time 194475733 ps
CPU time 1.97 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 198124 kb
Host smart-50fa134c-991f-4349-8e41-4b62745f54a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893481940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1893481940
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.4183369521
Short name T668
Test name
Test status
Simulation time 234160033 ps
CPU time 2.59 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:43:59 PM PDT 24
Peak memory 197152 kb
Host smart-68ba53b1-adac-4b5d-9ef7-4bbfd23ec26e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183369521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.4183369521
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2882896742
Short name T158
Test name
Test status
Simulation time 43972104 ps
CPU time 0.86 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:01 PM PDT 24
Peak memory 196064 kb
Host smart-b84ae004-1252-47b2-be71-54acd36de983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882896742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2882896742
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1072004082
Short name T460
Test name
Test status
Simulation time 14448291 ps
CPU time 0.64 seconds
Started Jul 19 04:44:07 PM PDT 24
Finished Jul 19 04:44:14 PM PDT 24
Peak memory 194300 kb
Host smart-291218b0-a1f3-449e-adea-55399c7ee44d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072004082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1072004082
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3212657965
Short name T270
Test name
Test status
Simulation time 205844456 ps
CPU time 3.26 seconds
Started Jul 19 04:43:58 PM PDT 24
Finished Jul 19 04:44:07 PM PDT 24
Peak memory 198224 kb
Host smart-80871610-b591-4fb9-8c28-2ad4ebeb0a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212657965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3212657965
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1643817131
Short name T223
Test name
Test status
Simulation time 306020695 ps
CPU time 1.27 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 196336 kb
Host smart-c01322e5-7fa2-455a-9bb7-8a3f2e9a846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643817131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1643817131
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2253249564
Short name T695
Test name
Test status
Simulation time 62935050 ps
CPU time 1.1 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 196728 kb
Host smart-af40ec30-e6ae-4457-9298-2a696fa25958
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253249564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2253249564
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.391642079
Short name T677
Test name
Test status
Simulation time 48968166417 ps
CPU time 58.68 seconds
Started Jul 19 04:43:47 PM PDT 24
Finished Jul 19 04:44:51 PM PDT 24
Peak memory 198264 kb
Host smart-4d6f7f52-de3d-40fe-96d7-ccd63e117f98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391642079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.391642079
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1159762713
Short name T584
Test name
Test status
Simulation time 17867369 ps
CPU time 0.63 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 194412 kb
Host smart-c06bdab1-1e26-4813-9fde-12aad3769266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159762713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1159762713
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.327629155
Short name T377
Test name
Test status
Simulation time 56039036 ps
CPU time 0.9 seconds
Started Jul 19 04:43:52 PM PDT 24
Finished Jul 19 04:43:57 PM PDT 24
Peak memory 197168 kb
Host smart-a854b748-cf12-40ba-88d9-e9739162d905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327629155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.327629155
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.453157968
Short name T339
Test name
Test status
Simulation time 3505487773 ps
CPU time 18.06 seconds
Started Jul 19 04:43:50 PM PDT 24
Finished Jul 19 04:44:12 PM PDT 24
Peak memory 197248 kb
Host smart-3f749d9c-0b3d-402f-9d30-f053ea96bc41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453157968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.453157968
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.611195252
Short name T30
Test name
Test status
Simulation time 169141755 ps
CPU time 1.01 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:43:58 PM PDT 24
Peak memory 196708 kb
Host smart-cd585ac0-dfb9-4798-983e-c101692f70fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611195252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.611195252
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2006028485
Short name T621
Test name
Test status
Simulation time 162982392 ps
CPU time 1.26 seconds
Started Jul 19 04:44:07 PM PDT 24
Finished Jul 19 04:44:15 PM PDT 24
Peak memory 197148 kb
Host smart-2f2f8098-0c00-4bd3-bcf3-d2086803b730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006028485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2006028485
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2623027496
Short name T299
Test name
Test status
Simulation time 67946241 ps
CPU time 1.5 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 196936 kb
Host smart-786f82b8-96e5-48c1-b96d-e4f4d7c85852
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623027496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2623027496
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1635510041
Short name T554
Test name
Test status
Simulation time 83315459 ps
CPU time 1.62 seconds
Started Jul 19 04:43:52 PM PDT 24
Finished Jul 19 04:43:57 PM PDT 24
Peak memory 196292 kb
Host smart-8a1f0f8c-5d8a-442f-87cb-7cc9257d608c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635510041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1635510041
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2807461165
Short name T253
Test name
Test status
Simulation time 25791628 ps
CPU time 0.88 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 196840 kb
Host smart-dc80a046-922d-4653-836d-7b7295fae7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807461165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2807461165
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2912999259
Short name T266
Test name
Test status
Simulation time 99255281 ps
CPU time 1.08 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 196008 kb
Host smart-60387ffb-b140-467b-8d9e-a37f8713ffba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912999259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2912999259
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2588450399
Short name T427
Test name
Test status
Simulation time 239024849 ps
CPU time 2.94 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 198136 kb
Host smart-cc961b49-bcbd-4619-ab08-07cbe1d2c605
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588450399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2588450399
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1077910284
Short name T636
Test name
Test status
Simulation time 249104607 ps
CPU time 1.19 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:43:57 PM PDT 24
Peak memory 196056 kb
Host smart-47b960a5-08ee-448c-ae0b-f1183f51bd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077910284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1077910284
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2689146680
Short name T121
Test name
Test status
Simulation time 148746791 ps
CPU time 1.04 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:01 PM PDT 24
Peak memory 195936 kb
Host smart-9a76bb2e-c266-426e-a58a-92b776f58bd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689146680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2689146680
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2819999862
Short name T394
Test name
Test status
Simulation time 33171620093 ps
CPU time 81.69 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:45:22 PM PDT 24
Peak memory 198324 kb
Host smart-a1e13955-379d-46ec-84b5-6819c8982043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819999862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2819999862
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.4095182681
Short name T634
Test name
Test status
Simulation time 58765154360 ps
CPU time 1616.77 seconds
Started Jul 19 04:43:54 PM PDT 24
Finished Jul 19 05:10:55 PM PDT 24
Peak memory 198448 kb
Host smart-1e0512c9-1814-4f3e-877c-19e23550b5fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4095182681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.4095182681
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1879151650
Short name T295
Test name
Test status
Simulation time 19963884 ps
CPU time 0.57 seconds
Started Jul 19 04:44:04 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 194288 kb
Host smart-f9e9fb1a-629d-47c6-9b81-4fb8489a93e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879151650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1879151650
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3077046010
Short name T698
Test name
Test status
Simulation time 48128016 ps
CPU time 0.88 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:09 PM PDT 24
Peak memory 196500 kb
Host smart-5eabe6e3-dfe6-400d-8820-f184968a6bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077046010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3077046010
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1621586575
Short name T599
Test name
Test status
Simulation time 202146859 ps
CPU time 9.51 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:17 PM PDT 24
Peak memory 196880 kb
Host smart-70ec7efd-f6bf-426d-8b77-1a728f9308c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621586575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1621586575
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2774137976
Short name T241
Test name
Test status
Simulation time 365052243 ps
CPU time 0.67 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:01 PM PDT 24
Peak memory 195852 kb
Host smart-397f68b4-562c-44ff-9ed3-23f1cd9d0123
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774137976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2774137976
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4288841148
Short name T197
Test name
Test status
Simulation time 28118704 ps
CPU time 0.7 seconds
Started Jul 19 04:43:54 PM PDT 24
Finished Jul 19 04:43:59 PM PDT 24
Peak memory 195520 kb
Host smart-53fc61af-a9c3-47cd-87de-6786a5acd97f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288841148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4288841148
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1539396313
Short name T233
Test name
Test status
Simulation time 29899483 ps
CPU time 1.23 seconds
Started Jul 19 04:43:54 PM PDT 24
Finished Jul 19 04:44:00 PM PDT 24
Peak memory 196912 kb
Host smart-525b6ff6-16b2-4f9a-9841-fddb41907957
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539396313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1539396313
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3869767920
Short name T433
Test name
Test status
Simulation time 104781198 ps
CPU time 1.05 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 195844 kb
Host smart-6ac3a33c-3277-4259-b86a-52007d96b316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869767920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3869767920
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2611246563
Short name T492
Test name
Test status
Simulation time 176501751 ps
CPU time 1.12 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:01 PM PDT 24
Peak memory 197220 kb
Host smart-e03aef5f-cfe4-47eb-b620-d5f2f71e4f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611246563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2611246563
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.72416660
Short name T583
Test name
Test status
Simulation time 61498630 ps
CPU time 1.19 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 197096 kb
Host smart-8d115109-d183-431a-af68-999b8712d86e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72416660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup_
pulldown.72416660
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2206355149
Short name T539
Test name
Test status
Simulation time 252662805 ps
CPU time 5.38 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:08 PM PDT 24
Peak memory 198208 kb
Host smart-52465633-1b7d-44e9-ba04-c3b0e161f871
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206355149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2206355149
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1112626134
Short name T155
Test name
Test status
Simulation time 102350019 ps
CPU time 0.89 seconds
Started Jul 19 04:43:58 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 196632 kb
Host smart-9271661c-d690-4ae4-b19f-a690509d0c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112626134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1112626134
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1358186671
Short name T608
Test name
Test status
Simulation time 68480859 ps
CPU time 1.34 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 196936 kb
Host smart-d2aa2d1e-3edf-4831-9e18-5aadc992a6d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358186671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1358186671
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3201644761
Short name T581
Test name
Test status
Simulation time 12572427896 ps
CPU time 71.26 seconds
Started Jul 19 04:43:52 PM PDT 24
Finished Jul 19 04:45:07 PM PDT 24
Peak memory 198272 kb
Host smart-e0bdf016-bff6-4d42-b928-814beca3e12f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201644761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3201644761
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.4190877702
Short name T512
Test name
Test status
Simulation time 114481092924 ps
CPU time 1596.89 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 05:10:43 PM PDT 24
Peak memory 198384 kb
Host smart-93e77dcf-7183-436b-a534-4b51c2b3d921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4190877702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.4190877702
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.402571087
Short name T574
Test name
Test status
Simulation time 22445481 ps
CPU time 0.6 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 194568 kb
Host smart-4538da05-72e0-410f-84a3-c13155314165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402571087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.402571087
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.4150143073
Short name T318
Test name
Test status
Simulation time 25191276 ps
CPU time 0.66 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 194208 kb
Host smart-82500c22-54c7-4d5d-978d-9c1ec9b4f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150143073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.4150143073
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3076345645
Short name T501
Test name
Test status
Simulation time 237538059 ps
CPU time 3.45 seconds
Started Jul 19 04:44:04 PM PDT 24
Finished Jul 19 04:44:15 PM PDT 24
Peak memory 195744 kb
Host smart-888ae2e8-468b-4a56-88d8-4647eed62ba7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076345645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3076345645
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.67894926
Short name T432
Test name
Test status
Simulation time 37260552 ps
CPU time 0.68 seconds
Started Jul 19 04:44:07 PM PDT 24
Finished Jul 19 04:44:15 PM PDT 24
Peak memory 194952 kb
Host smart-3797161b-5e38-40f8-be8e-a2451058a554
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67894926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.67894926
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1804510325
Short name T215
Test name
Test status
Simulation time 35943669 ps
CPU time 1.09 seconds
Started Jul 19 04:43:59 PM PDT 24
Finished Jul 19 04:44:07 PM PDT 24
Peak memory 196100 kb
Host smart-db8fd716-6fbd-4a87-8152-04b5b1be3748
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804510325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1804510325
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3656050055
Short name T353
Test name
Test status
Simulation time 312686963 ps
CPU time 2.96 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 198312 kb
Host smart-7b9b3879-d3c1-4eaf-9a48-f355bd7a261b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656050055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3656050055
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.765527932
Short name T122
Test name
Test status
Simulation time 137636210 ps
CPU time 2.51 seconds
Started Jul 19 04:44:04 PM PDT 24
Finished Jul 19 04:44:14 PM PDT 24
Peak memory 197304 kb
Host smart-c335c96c-c6a9-468f-bd17-fba72aa9c46d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765527932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
765527932
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3407581921
Short name T249
Test name
Test status
Simulation time 60914225 ps
CPU time 1.37 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 04:44:08 PM PDT 24
Peak memory 197120 kb
Host smart-0ef276ea-a4fa-4a4e-bd3b-b30b24625c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407581921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3407581921
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.719869349
Short name T449
Test name
Test status
Simulation time 37723417 ps
CPU time 0.65 seconds
Started Jul 19 04:44:12 PM PDT 24
Finished Jul 19 04:44:19 PM PDT 24
Peak memory 195112 kb
Host smart-e4285d62-4f62-4a5a-b8e6-ef06db72861e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719869349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.719869349
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.554662918
Short name T149
Test name
Test status
Simulation time 257233294 ps
CPU time 1.43 seconds
Started Jul 19 04:44:09 PM PDT 24
Finished Jul 19 04:44:17 PM PDT 24
Peak memory 198216 kb
Host smart-bbe2511d-04ec-45fe-8a33-975d559a4ec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554662918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.554662918
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3351077488
Short name T453
Test name
Test status
Simulation time 163394995 ps
CPU time 1.07 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 196460 kb
Host smart-9bf13bd8-e221-4b15-ab11-1d161f0a0dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351077488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3351077488
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2728949347
Short name T101
Test name
Test status
Simulation time 167964159 ps
CPU time 1.03 seconds
Started Jul 19 04:43:59 PM PDT 24
Finished Jul 19 04:44:06 PM PDT 24
Peak memory 195780 kb
Host smart-9956cf41-3360-4c81-b3be-580c9781e8e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728949347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2728949347
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4251691472
Short name T370
Test name
Test status
Simulation time 32521020450 ps
CPU time 179.96 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:47:09 PM PDT 24
Peak memory 198264 kb
Host smart-d2c2aaf2-cc76-4b92-bee7-4fd7d7f18167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251691472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4251691472
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1466183713
Short name T71
Test name
Test status
Simulation time 41066747096 ps
CPU time 1073.49 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 05:02:03 PM PDT 24
Peak memory 198524 kb
Host smart-552b4bef-0905-4cc5-96cd-3272aa13385e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1466183713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1466183713
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1275078359
Short name T43
Test name
Test status
Simulation time 35890945 ps
CPU time 0.58 seconds
Started Jul 19 04:44:16 PM PDT 24
Finished Jul 19 04:44:22 PM PDT 24
Peak memory 194220 kb
Host smart-a77be6e8-e90a-47db-bf0e-7a5c72314c7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275078359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1275078359
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2664440902
Short name T390
Test name
Test status
Simulation time 99868442 ps
CPU time 0.95 seconds
Started Jul 19 04:44:10 PM PDT 24
Finished Jul 19 04:44:18 PM PDT 24
Peak memory 197252 kb
Host smart-b51aec39-a1d8-444f-ac79-91707d6d6b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664440902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2664440902
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3210527677
Short name T522
Test name
Test status
Simulation time 2754152465 ps
CPU time 23.74 seconds
Started Jul 19 04:44:14 PM PDT 24
Finished Jul 19 04:44:43 PM PDT 24
Peak memory 197272 kb
Host smart-7b5d4258-4685-40bf-a007-b89c6b21dbdf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210527677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3210527677
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.725172779
Short name T495
Test name
Test status
Simulation time 110037423 ps
CPU time 0.83 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:13 PM PDT 24
Peak memory 196236 kb
Host smart-a7aaf5b6-99fc-4b58-b711-7057b6d5c07b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725172779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.725172779
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.4044071057
Short name T571
Test name
Test status
Simulation time 49210312 ps
CPU time 1.31 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:09 PM PDT 24
Peak memory 197212 kb
Host smart-9f7601ad-7725-4367-9b94-4fabe5cf83a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044071057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.4044071057
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4075524098
Short name T544
Test name
Test status
Simulation time 288023522 ps
CPU time 2.84 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:43:59 PM PDT 24
Peak memory 198264 kb
Host smart-f4525804-60ae-42cf-a37c-bcf9b00ea110
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075524098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4075524098
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3711251910
Short name T697
Test name
Test status
Simulation time 113123023 ps
CPU time 3.04 seconds
Started Jul 19 04:44:08 PM PDT 24
Finished Jul 19 04:44:18 PM PDT 24
Peak memory 196064 kb
Host smart-03328f21-9650-4841-82dc-717ba4920cce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711251910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3711251910
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1642118801
Short name T198
Test name
Test status
Simulation time 247530988 ps
CPU time 0.86 seconds
Started Jul 19 04:44:13 PM PDT 24
Finished Jul 19 04:44:20 PM PDT 24
Peak memory 196152 kb
Host smart-6951fe15-c3b5-485b-b75e-a4bfec11e329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642118801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1642118801
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.472733139
Short name T596
Test name
Test status
Simulation time 29576876 ps
CPU time 0.83 seconds
Started Jul 19 04:44:03 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 196784 kb
Host smart-f91a8fdc-a813-4f70-9907-8fda0e0c2667
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472733139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.472733139
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.902983662
Short name T423
Test name
Test status
Simulation time 724938588 ps
CPU time 2.1 seconds
Started Jul 19 04:44:09 PM PDT 24
Finished Jul 19 04:44:17 PM PDT 24
Peak memory 198216 kb
Host smart-bb8ff71f-66e7-49cd-828e-ff23665b0ad0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902983662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.902983662
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3291422975
Short name T406
Test name
Test status
Simulation time 99273740 ps
CPU time 1.32 seconds
Started Jul 19 04:44:03 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 195784 kb
Host smart-d16e8000-e38b-4d07-b436-452f80a51e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291422975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3291422975
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3591876716
Short name T521
Test name
Test status
Simulation time 274851739 ps
CPU time 1.06 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 195940 kb
Host smart-a10e58da-b882-44a9-9c47-71f87522171e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591876716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3591876716
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3784038661
Short name T559
Test name
Test status
Simulation time 10091151847 ps
CPU time 115.23 seconds
Started Jul 19 04:43:57 PM PDT 24
Finished Jul 19 04:45:58 PM PDT 24
Peak memory 198348 kb
Host smart-21cec2d6-a57c-4cd5-bab3-1ea9e3cad49f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784038661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3784038661
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.779215045
Short name T610
Test name
Test status
Simulation time 99966591792 ps
CPU time 633.12 seconds
Started Jul 19 04:44:07 PM PDT 24
Finished Jul 19 04:54:47 PM PDT 24
Peak memory 198412 kb
Host smart-c7883fb4-24ba-466e-b5d3-62d74950ce2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=779215045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.779215045
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1621236910
Short name T418
Test name
Test status
Simulation time 48792819 ps
CPU time 0.58 seconds
Started Jul 19 04:43:59 PM PDT 24
Finished Jul 19 04:44:06 PM PDT 24
Peak memory 194904 kb
Host smart-2ad00571-59c6-48c8-bfa6-2b8ceb85fd84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621236910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1621236910
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.987667197
Short name T632
Test name
Test status
Simulation time 116587671 ps
CPU time 0.8 seconds
Started Jul 19 04:44:12 PM PDT 24
Finished Jul 19 04:44:19 PM PDT 24
Peak memory 196216 kb
Host smart-8cca586c-1889-4dd9-944a-ae9a3838bc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987667197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.987667197
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.326792824
Short name T177
Test name
Test status
Simulation time 1757646817 ps
CPU time 22.63 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:31 PM PDT 24
Peak memory 196504 kb
Host smart-ea4fdf23-c56a-4391-86c6-ff0c682568ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326792824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.326792824
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1296692685
Short name T626
Test name
Test status
Simulation time 37416183 ps
CPU time 0.75 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 04:44:07 PM PDT 24
Peak memory 194920 kb
Host smart-cf3df64b-9bd3-48c4-8b81-2e93648d21e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296692685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1296692685
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2756507389
Short name T307
Test name
Test status
Simulation time 77169286 ps
CPU time 1.03 seconds
Started Jul 19 04:43:58 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 196176 kb
Host smart-88705496-3e55-490d-9efd-4fa5c83c0f13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756507389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2756507389
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2879994697
Short name T527
Test name
Test status
Simulation time 221763374 ps
CPU time 2.29 seconds
Started Jul 19 04:44:10 PM PDT 24
Finished Jul 19 04:44:19 PM PDT 24
Peak memory 198252 kb
Host smart-8eb4f457-d339-4533-9c5a-33157b2717e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879994697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2879994697
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2054600877
Short name T79
Test name
Test status
Simulation time 161882912 ps
CPU time 2 seconds
Started Jul 19 04:44:00 PM PDT 24
Finished Jul 19 04:44:08 PM PDT 24
Peak memory 195992 kb
Host smart-bbf5d67a-7591-41ec-bb35-b77d7baa6a15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054600877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2054600877
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2244043127
Short name T642
Test name
Test status
Simulation time 56686269 ps
CPU time 1.09 seconds
Started Jul 19 04:44:10 PM PDT 24
Finished Jul 19 04:44:17 PM PDT 24
Peak memory 196188 kb
Host smart-55358162-e68e-4422-8988-41a81d0190b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244043127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2244043127
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3515818757
Short name T131
Test name
Test status
Simulation time 535950410 ps
CPU time 1.18 seconds
Started Jul 19 04:43:58 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 198292 kb
Host smart-f7bf454c-84d6-406d-a831-d3e25602903d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515818757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3515818757
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.4145689177
Short name T588
Test name
Test status
Simulation time 1438520389 ps
CPU time 5.83 seconds
Started Jul 19 04:43:53 PM PDT 24
Finished Jul 19 04:44:03 PM PDT 24
Peak memory 198156 kb
Host smart-e087e772-028c-4ab6-ac0d-d95eb51a5eb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145689177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.4145689177
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2334122684
Short name T160
Test name
Test status
Simulation time 193494295 ps
CPU time 0.95 seconds
Started Jul 19 04:43:58 PM PDT 24
Finished Jul 19 04:44:04 PM PDT 24
Peak memory 195916 kb
Host smart-6500d9db-82ef-4e1a-903e-e0a5ef920a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334122684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2334122684
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4197844943
Short name T311
Test name
Test status
Simulation time 59030999 ps
CPU time 1.17 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:03 PM PDT 24
Peak memory 196012 kb
Host smart-69791ef0-f0c5-4336-915b-a2ef9ec4c04d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197844943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4197844943
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3518017289
Short name T54
Test name
Test status
Simulation time 5563834881 ps
CPU time 131.64 seconds
Started Jul 19 04:44:03 PM PDT 24
Finished Jul 19 04:46:21 PM PDT 24
Peak memory 198088 kb
Host smart-593139d5-364e-4900-b9c0-77c724f0911c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518017289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3518017289
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2002865131
Short name T385
Test name
Test status
Simulation time 50367802 ps
CPU time 0.57 seconds
Started Jul 19 04:44:03 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 194040 kb
Host smart-58b8f4eb-6522-446d-b00f-f94f1eaa22b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002865131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2002865131
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2498404631
Short name T456
Test name
Test status
Simulation time 143753571 ps
CPU time 0.68 seconds
Started Jul 19 04:44:09 PM PDT 24
Finished Jul 19 04:44:16 PM PDT 24
Peak memory 194204 kb
Host smart-96165e56-21dd-4d33-ae4b-6dd0406d6521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498404631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2498404631
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3569183463
Short name T412
Test name
Test status
Simulation time 697989629 ps
CPU time 19.77 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:20 PM PDT 24
Peak memory 197056 kb
Host smart-46f62e31-2d2b-4027-800a-c280874cf1fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569183463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3569183463
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2665300224
Short name T224
Test name
Test status
Simulation time 273375105 ps
CPU time 1.01 seconds
Started Jul 19 04:43:58 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 196768 kb
Host smart-5b65a88f-8373-4d23-8185-76bd77a6aa63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665300224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2665300224
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.682706425
Short name T374
Test name
Test status
Simulation time 283933604 ps
CPU time 1.29 seconds
Started Jul 19 04:44:02 PM PDT 24
Finished Jul 19 04:44:09 PM PDT 24
Peak memory 196144 kb
Host smart-99404115-97bb-4221-a59e-89a29fac6d47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682706425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.682706425
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4146995597
Short name T507
Test name
Test status
Simulation time 62257277 ps
CPU time 2.52 seconds
Started Jul 19 04:44:15 PM PDT 24
Finished Jul 19 04:44:23 PM PDT 24
Peak memory 198172 kb
Host smart-683ba3bb-31de-45e0-bd96-f44237505941
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146995597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4146995597
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.50163365
Short name T690
Test name
Test status
Simulation time 89266045 ps
CPU time 1.46 seconds
Started Jul 19 04:44:12 PM PDT 24
Finished Jul 19 04:44:19 PM PDT 24
Peak memory 196948 kb
Host smart-7f746432-727c-4e60-94f8-640f4473fd1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50163365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.50163365
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.129229382
Short name T56
Test name
Test status
Simulation time 50974814 ps
CPU time 1.03 seconds
Started Jul 19 04:44:09 PM PDT 24
Finished Jul 19 04:44:17 PM PDT 24
Peak memory 196992 kb
Host smart-48b2958f-e367-4eb3-adc8-593aa067917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129229382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.129229382
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2099484945
Short name T214
Test name
Test status
Simulation time 80813709 ps
CPU time 1.29 seconds
Started Jul 19 04:44:07 PM PDT 24
Finished Jul 19 04:44:15 PM PDT 24
Peak memory 197264 kb
Host smart-42c5dfb4-05b6-46fe-99f6-a88c3c6bf112
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099484945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2099484945
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.199976180
Short name T74
Test name
Test status
Simulation time 237431002 ps
CPU time 2.68 seconds
Started Jul 19 04:43:56 PM PDT 24
Finished Jul 19 04:44:03 PM PDT 24
Peak memory 198164 kb
Host smart-b4da0387-f63b-414c-9f09-e17961999032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199976180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.199976180
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1027590553
Short name T19
Test name
Test status
Simulation time 289152404 ps
CPU time 1.37 seconds
Started Jul 19 04:44:03 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 198024 kb
Host smart-2c57a0e5-a24e-40cb-9955-4068feba7f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027590553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1027590553
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2034232620
Short name T285
Test name
Test status
Simulation time 167288099 ps
CPU time 1.23 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:13 PM PDT 24
Peak memory 198272 kb
Host smart-23e99432-fc1b-4799-bd27-130d259ae7e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034232620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2034232620
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1349303271
Short name T382
Test name
Test status
Simulation time 6049479026 ps
CPU time 72.14 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:45:24 PM PDT 24
Peak memory 198344 kb
Host smart-585c1e43-19d4-4c55-871e-4788782030e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349303271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1349303271
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.656989273
Short name T529
Test name
Test status
Simulation time 28238403 ps
CPU time 0.76 seconds
Started Jul 19 04:44:14 PM PDT 24
Finished Jul 19 04:44:21 PM PDT 24
Peak memory 195360 kb
Host smart-2bf7f13e-808c-4fd2-9f8b-60dd713e225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656989273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.656989273
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3515839796
Short name T170
Test name
Test status
Simulation time 639158726 ps
CPU time 16.88 seconds
Started Jul 19 04:44:06 PM PDT 24
Finished Jul 19 04:44:30 PM PDT 24
Peak memory 197024 kb
Host smart-e37fc506-2e9f-4aaa-91fe-647dc5840879
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515839796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3515839796
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3260330315
Short name T140
Test name
Test status
Simulation time 214030256 ps
CPU time 0.85 seconds
Started Jul 19 04:44:12 PM PDT 24
Finished Jul 19 04:44:19 PM PDT 24
Peak memory 196120 kb
Host smart-acdef7fc-f994-47e9-9c4e-91f7d67494a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260330315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3260330315
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.947556485
Short name T464
Test name
Test status
Simulation time 79671642 ps
CPU time 1.15 seconds
Started Jul 19 04:44:14 PM PDT 24
Finished Jul 19 04:44:21 PM PDT 24
Peak memory 195984 kb
Host smart-9ea9222a-4e86-4848-b2bf-5f147869f8ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947556485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.947556485
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.440280682
Short name T603
Test name
Test status
Simulation time 52190960 ps
CPU time 1.11 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:13 PM PDT 24
Peak memory 197588 kb
Host smart-308dd241-0d2e-43a4-96c5-350c0c3bd883
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440280682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.440280682
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1373387070
Short name T94
Test name
Test status
Simulation time 110155319 ps
CPU time 0.93 seconds
Started Jul 19 04:44:17 PM PDT 24
Finished Jul 19 04:44:23 PM PDT 24
Peak memory 195540 kb
Host smart-cad1744a-6cbf-4c1a-ba00-55d7e6d5757b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373387070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1373387070
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3493721877
Short name T497
Test name
Test status
Simulation time 97270915 ps
CPU time 1.06 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:14 PM PDT 24
Peak memory 196772 kb
Host smart-5275aa3b-f9f5-49eb-91d9-ec109e3bd28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493721877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3493721877
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.424031999
Short name T314
Test name
Test status
Simulation time 97653679 ps
CPU time 1.13 seconds
Started Jul 19 04:44:03 PM PDT 24
Finished Jul 19 04:44:10 PM PDT 24
Peak memory 196876 kb
Host smart-e08c4b36-f7bb-496a-a62d-a3e636d2413a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424031999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.424031999
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.4138120069
Short name T3
Test name
Test status
Simulation time 347163275 ps
CPU time 4.53 seconds
Started Jul 19 04:44:07 PM PDT 24
Finished Jul 19 04:44:19 PM PDT 24
Peak memory 198032 kb
Host smart-e1ed4ec0-9148-432b-900e-923564c30fc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138120069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.4138120069
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3594614749
Short name T182
Test name
Test status
Simulation time 53225465 ps
CPU time 1.11 seconds
Started Jul 19 04:44:13 PM PDT 24
Finished Jul 19 04:44:20 PM PDT 24
Peak memory 195892 kb
Host smart-330ccae6-a777-410c-bbdd-256779a10e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594614749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3594614749
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3852083036
Short name T325
Test name
Test status
Simulation time 105401728 ps
CPU time 1.01 seconds
Started Jul 19 04:44:19 PM PDT 24
Finished Jul 19 04:44:24 PM PDT 24
Peak memory 196528 kb
Host smart-357abab9-9f7a-4b1f-8227-58e8fc1efd1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852083036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3852083036
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1706906932
Short name T676
Test name
Test status
Simulation time 9088703000 ps
CPU time 63.5 seconds
Started Jul 19 04:44:09 PM PDT 24
Finished Jul 19 04:45:19 PM PDT 24
Peak memory 198332 kb
Host smart-4c3a2b1a-f2c7-4cda-8fa0-d08f1b9d0996
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706906932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1706906932
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2856469293
Short name T62
Test name
Test status
Simulation time 71442311453 ps
CPU time 780.9 seconds
Started Jul 19 04:44:06 PM PDT 24
Finished Jul 19 04:57:14 PM PDT 24
Peak memory 198456 kb
Host smart-17c1a3b4-c9fe-4527-bfb4-4ef0973ae486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2856469293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2856469293
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2488562180
Short name T551
Test name
Test status
Simulation time 48694416 ps
CPU time 0.57 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:12 PM PDT 24
Peak memory 195916 kb
Host smart-12970d10-605c-4fc0-b09e-3d2611aeaebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488562180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2488562180
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.127600201
Short name T515
Test name
Test status
Simulation time 21670011 ps
CPU time 0.67 seconds
Started Jul 19 04:44:10 PM PDT 24
Finished Jul 19 04:44:17 PM PDT 24
Peak memory 194944 kb
Host smart-13e711f2-acdc-464a-8937-7f7634a06a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127600201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.127600201
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2724736751
Short name T682
Test name
Test status
Simulation time 430982648 ps
CPU time 5.25 seconds
Started Jul 19 04:44:09 PM PDT 24
Finished Jul 19 04:44:21 PM PDT 24
Peak memory 197128 kb
Host smart-97ca25fd-68a5-46e7-99c2-1568f7913a99
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724736751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2724736751
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.4080982080
Short name T502
Test name
Test status
Simulation time 67288842 ps
CPU time 0.79 seconds
Started Jul 19 04:44:11 PM PDT 24
Finished Jul 19 04:44:18 PM PDT 24
Peak memory 196096 kb
Host smart-2e7ea2bd-25e1-433e-8297-6ee0836ead7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080982080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4080982080
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.4049547774
Short name T673
Test name
Test status
Simulation time 69823264 ps
CPU time 1.17 seconds
Started Jul 19 04:44:10 PM PDT 24
Finished Jul 19 04:44:18 PM PDT 24
Peak memory 196308 kb
Host smart-23068232-9607-410b-8502-3ecbacdf58b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049547774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.4049547774
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3336554069
Short name T57
Test name
Test status
Simulation time 74643732 ps
CPU time 2.89 seconds
Started Jul 19 04:44:12 PM PDT 24
Finished Jul 19 04:44:21 PM PDT 24
Peak memory 198260 kb
Host smart-1a28d5a4-83e1-4218-847c-d9bf8f7153d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336554069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3336554069
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1482991767
Short name T308
Test name
Test status
Simulation time 180403273 ps
CPU time 1.51 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:09 PM PDT 24
Peak memory 196304 kb
Host smart-60055a30-5361-4bf7-94a9-c67cb4e48cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482991767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1482991767
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4069892997
Short name T237
Test name
Test status
Simulation time 21841458 ps
CPU time 0.81 seconds
Started Jul 19 04:44:24 PM PDT 24
Finished Jul 19 04:44:28 PM PDT 24
Peak memory 195756 kb
Host smart-5cd9d0ba-9078-48ec-ad64-dee9abf47dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069892997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4069892997
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.816519527
Short name T185
Test name
Test status
Simulation time 92123250 ps
CPU time 1.1 seconds
Started Jul 19 04:44:08 PM PDT 24
Finished Jul 19 04:44:16 PM PDT 24
Peak memory 196848 kb
Host smart-da68cfae-bad8-4431-8bcd-53f674f0a385
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816519527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.816519527
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2285496227
Short name T315
Test name
Test status
Simulation time 174414502 ps
CPU time 1.41 seconds
Started Jul 19 04:44:22 PM PDT 24
Finished Jul 19 04:44:27 PM PDT 24
Peak memory 198148 kb
Host smart-6c0ae15d-ad23-4b58-a9e4-197b13189409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285496227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2285496227
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2472603952
Short name T421
Test name
Test status
Simulation time 34499834 ps
CPU time 0.94 seconds
Started Jul 19 04:44:14 PM PDT 24
Finished Jul 19 04:44:21 PM PDT 24
Peak memory 195804 kb
Host smart-8b653a9a-daef-407a-8247-32b6b709ff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472603952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2472603952
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1011403321
Short name T286
Test name
Test status
Simulation time 82051192 ps
CPU time 1.45 seconds
Started Jul 19 04:44:10 PM PDT 24
Finished Jul 19 04:44:18 PM PDT 24
Peak memory 197284 kb
Host smart-744f8009-82b8-4530-9d37-07f494e5833c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011403321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1011403321
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.422258030
Short name T576
Test name
Test status
Simulation time 3967056848 ps
CPU time 96.55 seconds
Started Jul 19 04:44:17 PM PDT 24
Finished Jul 19 04:45:59 PM PDT 24
Peak memory 198288 kb
Host smart-12773f72-96fb-4832-9e20-4862e554daa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422258030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.422258030
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3965230303
Short name T661
Test name
Test status
Simulation time 12273718 ps
CPU time 0.57 seconds
Started Jul 19 04:43:17 PM PDT 24
Finished Jul 19 04:43:19 PM PDT 24
Peak memory 193948 kb
Host smart-6eaab8c6-fbbd-4cb3-a264-8b5d3198bf70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965230303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3965230303
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2747306064
Short name T436
Test name
Test status
Simulation time 19096197 ps
CPU time 0.64 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:33 PM PDT 24
Peak memory 194276 kb
Host smart-12c37bbc-4d5e-47d0-8145-3c85971f34df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747306064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2747306064
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1935872262
Short name T707
Test name
Test status
Simulation time 385077014 ps
CPU time 12.56 seconds
Started Jul 19 04:43:17 PM PDT 24
Finished Jul 19 04:43:32 PM PDT 24
Peak memory 196452 kb
Host smart-2eeff519-e04a-470c-969c-5a74f3e405a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935872262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1935872262
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2505296657
Short name T373
Test name
Test status
Simulation time 26023654 ps
CPU time 0.85 seconds
Started Jul 19 04:43:17 PM PDT 24
Finished Jul 19 04:43:20 PM PDT 24
Peak memory 195820 kb
Host smart-9783d772-2a34-4be5-b26a-ef5dded296fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505296657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2505296657
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3401593793
Short name T404
Test name
Test status
Simulation time 1285395884 ps
CPU time 3.19 seconds
Started Jul 19 04:43:17 PM PDT 24
Finished Jul 19 04:43:23 PM PDT 24
Peak memory 198288 kb
Host smart-daa548ed-905e-4904-8287-3fe7ce7b6219
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401593793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3401593793
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2106323351
Short name T624
Test name
Test status
Simulation time 568741394 ps
CPU time 1.29 seconds
Started Jul 19 04:43:20 PM PDT 24
Finished Jul 19 04:43:23 PM PDT 24
Peak memory 197428 kb
Host smart-cb88a3a9-3d04-4944-9165-09542c2a96ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106323351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2106323351
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.4174289808
Short name T593
Test name
Test status
Simulation time 20453808 ps
CPU time 0.86 seconds
Started Jul 19 04:43:23 PM PDT 24
Finished Jul 19 04:43:26 PM PDT 24
Peak memory 196072 kb
Host smart-f2a00226-4848-41e0-87b9-ff101cb7acd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174289808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.4174289808
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.432373293
Short name T696
Test name
Test status
Simulation time 104276005 ps
CPU time 1.04 seconds
Started Jul 19 04:43:24 PM PDT 24
Finished Jul 19 04:43:27 PM PDT 24
Peak memory 196168 kb
Host smart-f349402b-318e-4f89-b3d2-451ba8865aef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432373293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.432373293
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3174237767
Short name T711
Test name
Test status
Simulation time 1887478252 ps
CPU time 5.07 seconds
Started Jul 19 04:43:17 PM PDT 24
Finished Jul 19 04:43:25 PM PDT 24
Peak memory 198192 kb
Host smart-e4cfe9ff-5271-42ff-8f3a-c924c31f11f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174237767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3174237767
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1330364713
Short name T41
Test name
Test status
Simulation time 186007772 ps
CPU time 0.91 seconds
Started Jul 19 04:43:18 PM PDT 24
Finished Jul 19 04:43:22 PM PDT 24
Peak memory 214152 kb
Host smart-ed997a7b-bd2a-42d4-9c8d-51bfefd8e976
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330364713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1330364713
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3635016443
Short name T175
Test name
Test status
Simulation time 109116687 ps
CPU time 1.46 seconds
Started Jul 19 04:43:17 PM PDT 24
Finished Jul 19 04:43:20 PM PDT 24
Peak memory 196964 kb
Host smart-b1ae054e-4924-45df-84cd-09ab2eebbe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635016443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3635016443
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.4008212318
Short name T157
Test name
Test status
Simulation time 201948830 ps
CPU time 1.06 seconds
Started Jul 19 04:43:36 PM PDT 24
Finished Jul 19 04:43:43 PM PDT 24
Peak memory 195960 kb
Host smart-02a354ab-8fc8-4aee-9a16-18dbd40744e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008212318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.4008212318
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3071686671
Short name T589
Test name
Test status
Simulation time 26847604302 ps
CPU time 90.72 seconds
Started Jul 19 04:43:19 PM PDT 24
Finished Jul 19 04:44:53 PM PDT 24
Peak memory 198264 kb
Host smart-bd534d22-82b0-448d-9d4e-776f3d4d1a4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071686671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3071686671
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1423330635
Short name T139
Test name
Test status
Simulation time 56730390 ps
CPU time 0.6 seconds
Started Jul 19 04:44:19 PM PDT 24
Finished Jul 19 04:44:24 PM PDT 24
Peak memory 195084 kb
Host smart-4ba6c012-126f-4f9d-809b-a2284179ad18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423330635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1423330635
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.547342544
Short name T123
Test name
Test status
Simulation time 90141485 ps
CPU time 0.89 seconds
Started Jul 19 04:44:06 PM PDT 24
Finished Jul 19 04:44:14 PM PDT 24
Peak memory 197440 kb
Host smart-aa234837-bb36-4b87-80b8-d90eaf95a19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547342544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.547342544
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3479061976
Short name T347
Test name
Test status
Simulation time 477853601 ps
CPU time 15.9 seconds
Started Jul 19 04:44:16 PM PDT 24
Finished Jul 19 04:44:37 PM PDT 24
Peak memory 198180 kb
Host smart-31201022-9035-44f2-9549-4f1196847542
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479061976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3479061976
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1057587806
Short name T620
Test name
Test status
Simulation time 139179301 ps
CPU time 0.8 seconds
Started Jul 19 04:44:13 PM PDT 24
Finished Jul 19 04:44:20 PM PDT 24
Peak memory 196040 kb
Host smart-3d3e65db-2ebe-44ee-ac38-dc3401e982fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057587806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1057587806
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1885570387
Short name T530
Test name
Test status
Simulation time 67507278 ps
CPU time 1.12 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:44:08 PM PDT 24
Peak memory 196120 kb
Host smart-57393907-1054-4bdf-bc8e-8f0feab85b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885570387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1885570387
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3649117277
Short name T504
Test name
Test status
Simulation time 157650336 ps
CPU time 3.07 seconds
Started Jul 19 04:44:07 PM PDT 24
Finished Jul 19 04:44:18 PM PDT 24
Peak memory 197492 kb
Host smart-6a27c7cf-c255-4f00-9b10-518ee6e2744e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649117277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3649117277
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1194132181
Short name T217
Test name
Test status
Simulation time 590482659 ps
CPU time 1.85 seconds
Started Jul 19 04:44:13 PM PDT 24
Finished Jul 19 04:44:20 PM PDT 24
Peak memory 197484 kb
Host smart-21e9716c-9f10-44ec-8785-16ee778d85da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194132181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1194132181
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.4061171588
Short name T669
Test name
Test status
Simulation time 125474034 ps
CPU time 0.89 seconds
Started Jul 19 04:44:18 PM PDT 24
Finished Jul 19 04:44:24 PM PDT 24
Peak memory 196124 kb
Host smart-09414d74-2292-4425-9e8b-6202eb4af9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061171588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.4061171588
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3118761075
Short name T623
Test name
Test status
Simulation time 74560406 ps
CPU time 0.69 seconds
Started Jul 19 04:44:05 PM PDT 24
Finished Jul 19 04:44:12 PM PDT 24
Peak memory 195580 kb
Host smart-2bfb6b41-d3da-46fa-8004-c282c4df99f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118761075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3118761075
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.191273647
Short name T9
Test name
Test status
Simulation time 749826480 ps
CPU time 2.41 seconds
Started Jul 19 04:44:07 PM PDT 24
Finished Jul 19 04:44:17 PM PDT 24
Peak memory 198184 kb
Host smart-dfe2ea7a-b978-4e47-8b54-dfb1bc8d9e79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191273647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.191273647
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.522509998
Short name T607
Test name
Test status
Simulation time 160113590 ps
CPU time 1.19 seconds
Started Jul 19 04:44:12 PM PDT 24
Finished Jul 19 04:44:19 PM PDT 24
Peak memory 195976 kb
Host smart-d045ad72-b0d1-4ff3-860a-3428ab05e4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522509998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.522509998
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.148164210
Short name T33
Test name
Test status
Simulation time 150948845 ps
CPU time 1.15 seconds
Started Jul 19 04:44:16 PM PDT 24
Finished Jul 19 04:44:23 PM PDT 24
Peak memory 195788 kb
Host smart-90c352ef-8f30-4440-86b0-140f4469c2a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148164210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.148164210
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2817067787
Short name T234
Test name
Test status
Simulation time 12221842406 ps
CPU time 81.98 seconds
Started Jul 19 04:44:01 PM PDT 24
Finished Jul 19 04:45:29 PM PDT 24
Peak memory 198340 kb
Host smart-f21322ec-e316-4c3f-b36f-7a3f43720eff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817067787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2817067787
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1149978047
Short name T125
Test name
Test status
Simulation time 359428780223 ps
CPU time 2291.51 seconds
Started Jul 19 04:44:13 PM PDT 24
Finished Jul 19 05:22:30 PM PDT 24
Peak memory 198460 kb
Host smart-5983d677-1ff0-4419-9362-b79ca7f5cfa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1149978047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1149978047
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.265042638
Short name T440
Test name
Test status
Simulation time 16238610 ps
CPU time 0.6 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 04:44:31 PM PDT 24
Peak memory 194392 kb
Host smart-457b9035-4e5c-4654-8908-b74fee11c415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265042638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.265042638
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1555268394
Short name T454
Test name
Test status
Simulation time 20345524 ps
CPU time 0.68 seconds
Started Jul 19 04:44:10 PM PDT 24
Finished Jul 19 04:44:17 PM PDT 24
Peak memory 193440 kb
Host smart-b7714376-a6bb-4386-8baf-394c060f879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555268394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1555268394
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.823919205
Short name T478
Test name
Test status
Simulation time 351085242 ps
CPU time 18.94 seconds
Started Jul 19 04:44:21 PM PDT 24
Finished Jul 19 04:44:44 PM PDT 24
Peak memory 196992 kb
Host smart-ae50b7e2-0991-434e-a673-596684c6bf08
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823919205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.823919205
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.884665310
Short name T540
Test name
Test status
Simulation time 213034250 ps
CPU time 0.83 seconds
Started Jul 19 04:44:20 PM PDT 24
Finished Jul 19 04:44:25 PM PDT 24
Peak memory 196824 kb
Host smart-bc86ff02-df54-4521-a8e0-9fba9f06f955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884665310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.884665310
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2593952472
Short name T195
Test name
Test status
Simulation time 64434049 ps
CPU time 1.06 seconds
Started Jul 19 04:44:11 PM PDT 24
Finished Jul 19 04:44:18 PM PDT 24
Peak memory 196040 kb
Host smart-6dab1a1c-4568-4c39-9859-a5f45a70fe7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593952472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2593952472
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1974803166
Short name T208
Test name
Test status
Simulation time 224804945 ps
CPU time 3 seconds
Started Jul 19 04:44:17 PM PDT 24
Finished Jul 19 04:44:25 PM PDT 24
Peak memory 198272 kb
Host smart-8be5395c-15db-4d4c-9a8d-d749428c69f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974803166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1974803166
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2713296336
Short name T549
Test name
Test status
Simulation time 290123650 ps
CPU time 1.71 seconds
Started Jul 19 04:44:22 PM PDT 24
Finished Jul 19 04:44:27 PM PDT 24
Peak memory 196300 kb
Host smart-9ead4794-dd89-45dd-b707-fb4e052fc1dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713296336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2713296336
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1539089300
Short name T102
Test name
Test status
Simulation time 165676759 ps
CPU time 1.15 seconds
Started Jul 19 04:44:16 PM PDT 24
Finished Jul 19 04:44:23 PM PDT 24
Peak memory 196416 kb
Host smart-aadbf71e-ef4b-4ad2-86d8-386710f3d36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539089300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1539089300
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.482428865
Short name T356
Test name
Test status
Simulation time 57455129 ps
CPU time 1.15 seconds
Started Jul 19 04:44:17 PM PDT 24
Finished Jul 19 04:44:23 PM PDT 24
Peak memory 197040 kb
Host smart-d8c03357-a266-4dc1-b63d-d8129e5019c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482428865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.482428865
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.66398672
Short name T148
Test name
Test status
Simulation time 200907141 ps
CPU time 3.66 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:37 PM PDT 24
Peak memory 198096 kb
Host smart-d53b50f4-4375-4655-b14d-af0ddf23a3c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66398672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand
om_long_reg_writes_reg_reads.66398672
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1232145776
Short name T313
Test name
Test status
Simulation time 243229516 ps
CPU time 0.8 seconds
Started Jul 19 04:44:10 PM PDT 24
Finished Jul 19 04:44:17 PM PDT 24
Peak memory 196152 kb
Host smart-5a0f18a9-59ac-44e6-9f8f-ade5e80efd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232145776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1232145776
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.120039297
Short name T517
Test name
Test status
Simulation time 175777379 ps
CPU time 1.23 seconds
Started Jul 19 04:44:14 PM PDT 24
Finished Jul 19 04:44:21 PM PDT 24
Peak memory 197148 kb
Host smart-318a3d15-cfe5-4bf6-b655-a5655128e5dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120039297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.120039297
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3420873798
Short name T366
Test name
Test status
Simulation time 13899002459 ps
CPU time 148.22 seconds
Started Jul 19 04:44:16 PM PDT 24
Finished Jul 19 04:46:50 PM PDT 24
Peak memory 198328 kb
Host smart-ef93f6e2-3832-4aca-bc1a-d74103ebe342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420873798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3420873798
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.242293849
Short name T29
Test name
Test status
Simulation time 29628665 ps
CPU time 0.58 seconds
Started Jul 19 04:44:20 PM PDT 24
Finished Jul 19 04:44:25 PM PDT 24
Peak memory 194896 kb
Host smart-99d682ba-b642-4e8f-9f78-46cb1727d8f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242293849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.242293849
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.610575382
Short name T303
Test name
Test status
Simulation time 122830339 ps
CPU time 0.68 seconds
Started Jul 19 04:44:19 PM PDT 24
Finished Jul 19 04:44:24 PM PDT 24
Peak memory 194292 kb
Host smart-0480b0ae-8f58-4224-9ea3-40fc56664986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610575382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.610575382
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3933652480
Short name T415
Test name
Test status
Simulation time 2704315291 ps
CPU time 5.8 seconds
Started Jul 19 04:44:19 PM PDT 24
Finished Jul 19 04:44:29 PM PDT 24
Peak memory 198296 kb
Host smart-835edcb1-09a4-466b-943c-a025ae9892c2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933652480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3933652480
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2915674333
Short name T284
Test name
Test status
Simulation time 147108899 ps
CPU time 0.76 seconds
Started Jul 19 04:44:16 PM PDT 24
Finished Jul 19 04:44:22 PM PDT 24
Peak memory 195640 kb
Host smart-6c287788-a2d3-4860-8cd5-e4e534e64a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915674333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2915674333
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3152323269
Short name T199
Test name
Test status
Simulation time 92846272 ps
CPU time 0.94 seconds
Started Jul 19 04:44:20 PM PDT 24
Finished Jul 19 04:44:25 PM PDT 24
Peak memory 196152 kb
Host smart-edb3ad01-0d3c-4d11-b23a-6856d8192e39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152323269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3152323269
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.4211886022
Short name T116
Test name
Test status
Simulation time 302951975 ps
CPU time 2.94 seconds
Started Jul 19 04:44:21 PM PDT 24
Finished Jul 19 04:44:28 PM PDT 24
Peak memory 198288 kb
Host smart-3de2da51-a2e5-4b30-9a1b-cfe1dbd54928
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211886022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.4211886022
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3315965607
Short name T261
Test name
Test status
Simulation time 31879721 ps
CPU time 0.95 seconds
Started Jul 19 04:44:17 PM PDT 24
Finished Jul 19 04:44:23 PM PDT 24
Peak memory 195720 kb
Host smart-791782c2-6e71-4af7-96da-0af37c5dcc2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315965607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3315965607
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3740523483
Short name T204
Test name
Test status
Simulation time 28524450 ps
CPU time 0.84 seconds
Started Jul 19 04:44:17 PM PDT 24
Finished Jul 19 04:44:23 PM PDT 24
Peak memory 197452 kb
Host smart-5c86c4a1-f938-4cc4-b5e2-c5339412114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740523483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3740523483
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3501920396
Short name T523
Test name
Test status
Simulation time 59351350 ps
CPU time 0.75 seconds
Started Jul 19 04:44:15 PM PDT 24
Finished Jul 19 04:44:22 PM PDT 24
Peak memory 195624 kb
Host smart-c924bb54-1c60-4ee9-a508-064829f666ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501920396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3501920396
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1192671039
Short name T166
Test name
Test status
Simulation time 341248610 ps
CPU time 5.53 seconds
Started Jul 19 04:44:15 PM PDT 24
Finished Jul 19 04:44:26 PM PDT 24
Peak memory 198216 kb
Host smart-237afb1e-84b4-43a1-8ebb-c0816a3e698d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192671039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1192671039
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2090984445
Short name T239
Test name
Test status
Simulation time 93504028 ps
CPU time 0.95 seconds
Started Jul 19 04:44:24 PM PDT 24
Finished Jul 19 04:44:28 PM PDT 24
Peak memory 196500 kb
Host smart-b040aac3-0aff-4840-8b03-9e0b39b2a8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090984445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2090984445
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2116546564
Short name T409
Test name
Test status
Simulation time 52965955 ps
CPU time 1.14 seconds
Started Jul 19 04:44:18 PM PDT 24
Finished Jul 19 04:44:24 PM PDT 24
Peak memory 195828 kb
Host smart-a4394007-9eda-4725-8c25-bb15edf5afa5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116546564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2116546564
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.862437645
Short name T490
Test name
Test status
Simulation time 7800047986 ps
CPU time 77.68 seconds
Started Jul 19 04:44:24 PM PDT 24
Finished Jul 19 04:45:44 PM PDT 24
Peak memory 198476 kb
Host smart-2a9c3ef1-4f2f-409f-ba54-85c093ff2936
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862437645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.862437645
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.870287133
Short name T66
Test name
Test status
Simulation time 205110532409 ps
CPU time 2169.91 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 05:20:45 PM PDT 24
Peak memory 198496 kb
Host smart-2dd93626-946e-4ffa-ae71-a186084e021d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=870287133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.870287133
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1077878324
Short name T219
Test name
Test status
Simulation time 23473579 ps
CPU time 0.61 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:33 PM PDT 24
Peak memory 194160 kb
Host smart-25834471-ab4f-4b4a-8290-3151f5e1d3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077878324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1077878324
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3208858163
Short name T658
Test name
Test status
Simulation time 34359325 ps
CPU time 0.85 seconds
Started Jul 19 04:44:24 PM PDT 24
Finished Jul 19 04:44:29 PM PDT 24
Peak memory 195588 kb
Host smart-43e10c9a-b5c6-4804-aaeb-1b0cd3844e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208858163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3208858163
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.749897963
Short name T680
Test name
Test status
Simulation time 894888857 ps
CPU time 23.79 seconds
Started Jul 19 04:44:26 PM PDT 24
Finished Jul 19 04:44:53 PM PDT 24
Peak memory 196472 kb
Host smart-0c32589e-b452-4ba8-b2db-c944f9cb46b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749897963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.749897963
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2519557267
Short name T220
Test name
Test status
Simulation time 30360059 ps
CPU time 0.66 seconds
Started Jul 19 04:44:18 PM PDT 24
Finished Jul 19 04:44:23 PM PDT 24
Peak memory 194680 kb
Host smart-b5c3d10c-6f35-494f-8e33-f5f7a1b76d02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519557267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2519557267
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.567976740
Short name T333
Test name
Test status
Simulation time 311700513 ps
CPU time 1.41 seconds
Started Jul 19 04:44:19 PM PDT 24
Finished Jul 19 04:44:25 PM PDT 24
Peak memory 196072 kb
Host smart-c9f9113b-afe3-40a7-bf5c-55f6289e9fa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567976740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.567976740
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3712621183
Short name T371
Test name
Test status
Simulation time 88651906 ps
CPU time 3.4 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 198220 kb
Host smart-e52e1d79-ade8-459d-ab40-fdc6173055ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712621183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3712621183
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.951818983
Short name T710
Test name
Test status
Simulation time 83099035 ps
CPU time 1.71 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:37 PM PDT 24
Peak memory 197064 kb
Host smart-9b42d0a0-29cf-4c25-b4d2-96ff15c26440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951818983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
951818983
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2960853367
Short name T705
Test name
Test status
Simulation time 78441125 ps
CPU time 0.75 seconds
Started Jul 19 04:44:21 PM PDT 24
Finished Jul 19 04:44:25 PM PDT 24
Peak memory 195464 kb
Host smart-127bf00f-2ee0-4513-9e3f-cd2ee080f134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960853367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2960853367
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1224167955
Short name T399
Test name
Test status
Simulation time 17947228 ps
CPU time 0.76 seconds
Started Jul 19 04:44:22 PM PDT 24
Finished Jul 19 04:44:26 PM PDT 24
Peak memory 195700 kb
Host smart-cb2d2d67-29e5-425a-afa0-ef68488e28ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224167955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1224167955
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.4081740338
Short name T687
Test name
Test status
Simulation time 120252778 ps
CPU time 2.24 seconds
Started Jul 19 04:44:24 PM PDT 24
Finished Jul 19 04:44:30 PM PDT 24
Peak memory 198176 kb
Host smart-180dbc5e-95ce-4943-9c1f-73c85938c13d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081740338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.4081740338
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.4280969439
Short name T296
Test name
Test status
Simulation time 276308329 ps
CPU time 1.3 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 04:44:32 PM PDT 24
Peak memory 196840 kb
Host smart-76b4bb49-da55-4730-8963-323101be5469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280969439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.4280969439
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3492106900
Short name T693
Test name
Test status
Simulation time 180876642 ps
CPU time 1.22 seconds
Started Jul 19 04:44:16 PM PDT 24
Finished Jul 19 04:44:22 PM PDT 24
Peak memory 195716 kb
Host smart-b302cda2-db3b-4e37-9f5b-874c7c393481
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492106900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3492106900
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.815488123
Short name T513
Test name
Test status
Simulation time 88026894706 ps
CPU time 132.91 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 04:46:44 PM PDT 24
Peak memory 198368 kb
Host smart-50960a52-db8e-48fe-a4d3-331a034ddc58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815488123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.815488123
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2579387852
Short name T301
Test name
Test status
Simulation time 13822937 ps
CPU time 0.58 seconds
Started Jul 19 04:44:23 PM PDT 24
Finished Jul 19 04:44:27 PM PDT 24
Peak memory 194848 kb
Host smart-1e6436ad-0108-4762-bc6a-39a11f90ac52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579387852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2579387852
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3678856324
Short name T398
Test name
Test status
Simulation time 72178987 ps
CPU time 0.9 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 196664 kb
Host smart-94319705-ce83-4852-826a-3f565fb2f462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678856324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3678856324
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2124697312
Short name T344
Test name
Test status
Simulation time 5052470673 ps
CPU time 21.94 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:59 PM PDT 24
Peak memory 197680 kb
Host smart-74ee69ac-04e7-439d-ac5d-5326302409a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124697312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2124697312
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3907744036
Short name T8
Test name
Test status
Simulation time 156754778 ps
CPU time 1.07 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 196860 kb
Host smart-cb6d8ad3-5d3b-4d37-a0bf-7156b9fcc85e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907744036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3907744036
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1380884049
Short name T129
Test name
Test status
Simulation time 334625629 ps
CPU time 1.46 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 04:44:33 PM PDT 24
Peak memory 197156 kb
Host smart-22c48339-db74-4f08-af19-6ff001d102c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380884049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1380884049
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2074449502
Short name T475
Test name
Test status
Simulation time 189821530 ps
CPU time 1.92 seconds
Started Jul 19 04:44:25 PM PDT 24
Finished Jul 19 04:44:30 PM PDT 24
Peak memory 198176 kb
Host smart-e6f0f1aa-b091-42e7-a0cc-1009d8a0ac81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074449502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2074449502
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1746602708
Short name T332
Test name
Test status
Simulation time 107307511 ps
CPU time 2.92 seconds
Started Jul 19 04:44:34 PM PDT 24
Finished Jul 19 04:44:44 PM PDT 24
Peak memory 197204 kb
Host smart-6779c414-32ed-4705-80e2-e98bbebbc376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746602708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1746602708
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2545729001
Short name T76
Test name
Test status
Simulation time 134444813 ps
CPU time 0.78 seconds
Started Jul 19 04:44:25 PM PDT 24
Finished Jul 19 04:44:29 PM PDT 24
Peak memory 195500 kb
Host smart-57d7f119-b83a-4090-81a0-7ecab3ac90e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545729001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2545729001
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1231356868
Short name T77
Test name
Test status
Simulation time 332679522 ps
CPU time 1.11 seconds
Started Jul 19 04:44:22 PM PDT 24
Finished Jul 19 04:44:27 PM PDT 24
Peak memory 196180 kb
Host smart-6d35bb24-b4c3-45a2-b601-ac3c3dd9e7eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231356868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1231356868
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2750283163
Short name T703
Test name
Test status
Simulation time 235001361 ps
CPU time 3.58 seconds
Started Jul 19 04:44:32 PM PDT 24
Finished Jul 19 04:44:43 PM PDT 24
Peak memory 198164 kb
Host smart-a756c9d6-089b-4726-ab66-78efa3bd91d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750283163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2750283163
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.727332104
Short name T463
Test name
Test status
Simulation time 101210115 ps
CPU time 0.94 seconds
Started Jul 19 04:44:33 PM PDT 24
Finished Jul 19 04:44:41 PM PDT 24
Peak memory 195904 kb
Host smart-b01092ef-0c86-4c6d-a425-ad66d28f2229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727332104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.727332104
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2486660986
Short name T401
Test name
Test status
Simulation time 40924002 ps
CPU time 0.9 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 196484 kb
Host smart-bb8c31eb-a5cd-48a5-848a-e237e4366a01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486660986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2486660986
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.215169475
Short name T161
Test name
Test status
Simulation time 86615374784 ps
CPU time 199.59 seconds
Started Jul 19 04:44:22 PM PDT 24
Finished Jul 19 04:47:45 PM PDT 24
Peak memory 198292 kb
Host smart-a580dc60-5330-48e9-bd3f-19b25c4c6ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215169475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.215169475
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.175197158
Short name T625
Test name
Test status
Simulation time 266641845180 ps
CPU time 1069.13 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 05:02:20 PM PDT 24
Peak memory 198480 kb
Host smart-01d691c2-2d61-483c-b2f9-3b84d6795552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=175197158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.175197158
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1448760748
Short name T493
Test name
Test status
Simulation time 14707101 ps
CPU time 0.64 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:33 PM PDT 24
Peak memory 194904 kb
Host smart-08643e7d-753f-43d7-8aa0-e74b80f54fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448760748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1448760748
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2293581727
Short name T594
Test name
Test status
Simulation time 161940077 ps
CPU time 0.77 seconds
Started Jul 19 04:44:33 PM PDT 24
Finished Jul 19 04:44:40 PM PDT 24
Peak memory 195472 kb
Host smart-dcf2a98d-c51d-43be-b24f-5cc585e93b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293581727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2293581727
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2483462363
Short name T282
Test name
Test status
Simulation time 1051710981 ps
CPU time 26.35 seconds
Started Jul 19 04:44:33 PM PDT 24
Finished Jul 19 04:45:06 PM PDT 24
Peak memory 196964 kb
Host smart-60a51845-d702-4686-b72f-23cb5565fb18
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483462363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2483462363
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2801747771
Short name T163
Test name
Test status
Simulation time 80859214 ps
CPU time 0.98 seconds
Started Jul 19 04:44:21 PM PDT 24
Finished Jul 19 04:44:26 PM PDT 24
Peak memory 197112 kb
Host smart-ea81e29a-b636-4bea-b91a-62a611b266a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801747771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2801747771
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.472751308
Short name T666
Test name
Test status
Simulation time 80338346 ps
CPU time 0.89 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:37 PM PDT 24
Peak memory 196928 kb
Host smart-4c02d8f0-77b5-4e46-b294-cec927cbf7fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472751308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.472751308
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.199308478
Short name T236
Test name
Test status
Simulation time 279452888 ps
CPU time 2.76 seconds
Started Jul 19 04:44:32 PM PDT 24
Finished Jul 19 04:44:42 PM PDT 24
Peak memory 198328 kb
Host smart-a10e12fe-1cde-4a8e-b884-bbdaf9c7ad38
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199308478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.199308478
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1005696996
Short name T628
Test name
Test status
Simulation time 103460701 ps
CPU time 1.92 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:35 PM PDT 24
Peak memory 197060 kb
Host smart-1cd36fa7-9b30-4184-9b00-0ea34c2d2c79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005696996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1005696996
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.474059067
Short name T647
Test name
Test status
Simulation time 56309500 ps
CPU time 1.26 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 198264 kb
Host smart-4a73a81f-0136-4536-ab42-b84366926f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474059067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.474059067
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4160745665
Short name T304
Test name
Test status
Simulation time 59180156 ps
CPU time 1.1 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 196752 kb
Host smart-8f638681-a2f4-4883-b1aa-93cd41b8f00f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160745665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.4160745665
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1297136376
Short name T645
Test name
Test status
Simulation time 517602570 ps
CPU time 6.88 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:42 PM PDT 24
Peak memory 198148 kb
Host smart-2efedd61-1685-4495-bf08-5949847dcdbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297136376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1297136376
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1350783192
Short name T570
Test name
Test status
Simulation time 186677547 ps
CPU time 1.2 seconds
Started Jul 19 04:44:24 PM PDT 24
Finished Jul 19 04:44:28 PM PDT 24
Peak memory 195792 kb
Host smart-c6c28912-bd08-4ff1-ae61-6643d4c9d67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350783192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1350783192
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3689268426
Short name T340
Test name
Test status
Simulation time 193690135 ps
CPU time 0.94 seconds
Started Jul 19 04:44:32 PM PDT 24
Finished Jul 19 04:44:41 PM PDT 24
Peak memory 195564 kb
Host smart-1b7a9f0b-91ed-4af2-86e0-f170a728ea6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689268426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3689268426
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.249296294
Short name T117
Test name
Test status
Simulation time 29104596231 ps
CPU time 192.28 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:47:50 PM PDT 24
Peak memory 198320 kb
Host smart-fd58f143-b8af-466c-ab7c-f9915fb2c6e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249296294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.249296294
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2894849611
Short name T681
Test name
Test status
Simulation time 22848656 ps
CPU time 0.58 seconds
Started Jul 19 04:44:26 PM PDT 24
Finished Jul 19 04:44:31 PM PDT 24
Peak memory 194188 kb
Host smart-4c60bb2e-d8e1-408b-b340-3cda8fbf37b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894849611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2894849611
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.292358298
Short name T271
Test name
Test status
Simulation time 85212056 ps
CPU time 0.7 seconds
Started Jul 19 04:44:26 PM PDT 24
Finished Jul 19 04:44:30 PM PDT 24
Peak memory 194308 kb
Host smart-09ffe237-d57e-411d-aca3-34807d216827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292358298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.292358298
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3369039303
Short name T256
Test name
Test status
Simulation time 3383415787 ps
CPU time 24.9 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:58 PM PDT 24
Peak memory 198168 kb
Host smart-ed0a8c8c-f869-4799-80f4-7c1e05dc4652
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369039303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3369039303
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3022466766
Short name T210
Test name
Test status
Simulation time 41047936 ps
CPU time 0.71 seconds
Started Jul 19 04:44:31 PM PDT 24
Finished Jul 19 04:44:38 PM PDT 24
Peak memory 194868 kb
Host smart-9e114c84-9ffc-4153-9045-10d1a005f56d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022466766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3022466766
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1710290483
Short name T357
Test name
Test status
Simulation time 51472753 ps
CPU time 0.93 seconds
Started Jul 19 04:44:25 PM PDT 24
Finished Jul 19 04:44:29 PM PDT 24
Peak memory 197020 kb
Host smart-75bbae1f-7740-413f-bb96-b6b0413c49ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710290483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1710290483
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.977435434
Short name T128
Test name
Test status
Simulation time 52354958 ps
CPU time 1.14 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 196852 kb
Host smart-3f01f2e8-1444-424b-8d24-b062566732ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977435434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.977435434
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.365242638
Short name T708
Test name
Test status
Simulation time 283702607 ps
CPU time 2.34 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 196048 kb
Host smart-d0739844-1086-4caf-89a8-72fa891a0230
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365242638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
365242638
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2661698010
Short name T466
Test name
Test status
Simulation time 131858697 ps
CPU time 0.83 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 196044 kb
Host smart-c0f0a5f4-e543-4b4c-9662-4f76ceab0864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661698010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2661698010
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.72971305
Short name T135
Test name
Test status
Simulation time 20987291 ps
CPU time 0.91 seconds
Started Jul 19 04:44:21 PM PDT 24
Finished Jul 19 04:44:26 PM PDT 24
Peak memory 196768 kb
Host smart-749cd351-ab70-4d68-9969-3808e286db4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72971305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup_
pulldown.72971305
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2849189265
Short name T630
Test name
Test status
Simulation time 205031190 ps
CPU time 1.7 seconds
Started Jul 19 04:44:41 PM PDT 24
Finished Jul 19 04:44:48 PM PDT 24
Peak memory 198172 kb
Host smart-bcafaf17-aa3f-4482-8a04-c4363ccab9f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849189265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2849189265
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.369039905
Short name T288
Test name
Test status
Simulation time 63562069 ps
CPU time 1.33 seconds
Started Jul 19 04:44:21 PM PDT 24
Finished Jul 19 04:44:26 PM PDT 24
Peak memory 197152 kb
Host smart-f23ef46d-d1dc-4889-9931-db83bc17a9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369039905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.369039905
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1943978094
Short name T447
Test name
Test status
Simulation time 165401992 ps
CPU time 1.1 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:37 PM PDT 24
Peak memory 196804 kb
Host smart-7a94eb00-c690-42ba-8bb0-2e394b1e896c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943978094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1943978094
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1927812799
Short name T458
Test name
Test status
Simulation time 12284079927 ps
CPU time 131.72 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:46:47 PM PDT 24
Peak memory 198368 kb
Host smart-66ed16fd-5902-45ea-9116-a901ea15dd6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927812799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1927812799
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.218981300
Short name T27
Test name
Test status
Simulation time 13729359 ps
CPU time 0.58 seconds
Started Jul 19 04:44:33 PM PDT 24
Finished Jul 19 04:44:40 PM PDT 24
Peak memory 192936 kb
Host smart-5800b1a6-5c7e-4154-b0d1-24b4fec4a5aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218981300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.218981300
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3768391149
Short name T265
Test name
Test status
Simulation time 26307110 ps
CPU time 0.84 seconds
Started Jul 19 04:44:26 PM PDT 24
Finished Jul 19 04:44:31 PM PDT 24
Peak memory 195460 kb
Host smart-01481628-9e60-4f93-b8f0-7634991a4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768391149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3768391149
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1319822853
Short name T629
Test name
Test status
Simulation time 533242977 ps
CPU time 5.89 seconds
Started Jul 19 04:44:34 PM PDT 24
Finished Jul 19 04:44:46 PM PDT 24
Peak memory 195716 kb
Host smart-252e68d8-63d6-4804-a5e3-70cb70462c71
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319822853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1319822853
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4065521196
Short name T422
Test name
Test status
Simulation time 131130798 ps
CPU time 0.97 seconds
Started Jul 19 04:44:24 PM PDT 24
Finished Jul 19 04:44:29 PM PDT 24
Peak memory 196964 kb
Host smart-7a857141-72eb-455e-b3a5-0a8870cf4d81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065521196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4065521196
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1819579006
Short name T617
Test name
Test status
Simulation time 547697509 ps
CPU time 1.04 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 04:44:33 PM PDT 24
Peak memory 196244 kb
Host smart-a9bcf656-feac-4a9b-96b1-69b81a0551f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819579006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1819579006
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1834065050
Short name T322
Test name
Test status
Simulation time 282642624 ps
CPU time 2.94 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:39 PM PDT 24
Peak memory 197472 kb
Host smart-5efa7f27-7fc5-414a-a60f-c36bedf42d95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834065050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1834065050
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.473087357
Short name T336
Test name
Test status
Simulation time 161088099 ps
CPU time 1.09 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 195784 kb
Host smart-4a07f477-1994-4bd0-b63b-c2a1051de288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473087357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
473087357
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1379770792
Short name T218
Test name
Test status
Simulation time 30352204 ps
CPU time 1.09 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:37 PM PDT 24
Peak memory 196276 kb
Host smart-9bb3c97f-055c-4db4-935a-5c8d83b6e9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379770792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1379770792
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.921683974
Short name T564
Test name
Test status
Simulation time 55931338 ps
CPU time 1.06 seconds
Started Jul 19 04:44:32 PM PDT 24
Finished Jul 19 04:44:40 PM PDT 24
Peak memory 195996 kb
Host smart-6d595503-2ae9-450b-838d-85eeba8ea0e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921683974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.921683974
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.382152108
Short name T23
Test name
Test status
Simulation time 145009263 ps
CPU time 3.09 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:40 PM PDT 24
Peak memory 198172 kb
Host smart-13e2fe17-7a4b-4fc3-90c6-21586a702b58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382152108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.382152108
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1906682883
Short name T337
Test name
Test status
Simulation time 272853361 ps
CPU time 1.37 seconds
Started Jul 19 04:44:26 PM PDT 24
Finished Jul 19 04:44:31 PM PDT 24
Peak memory 196968 kb
Host smart-52e2aabf-a38f-430e-9df4-2baff34b1c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906682883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1906682883
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2010585104
Short name T136
Test name
Test status
Simulation time 213575423 ps
CPU time 1.11 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:39 PM PDT 24
Peak memory 195960 kb
Host smart-041ed2fd-9d8d-4bf3-8f61-ad59af79166c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010585104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2010585104
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.4126227428
Short name T329
Test name
Test status
Simulation time 10614827477 ps
CPU time 68.5 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:45:45 PM PDT 24
Peak memory 198352 kb
Host smart-4bce5828-be3a-44e9-88d8-66884dc11822
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126227428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.4126227428
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2987829103
Short name T643
Test name
Test status
Simulation time 44921072 ps
CPU time 0.56 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 194884 kb
Host smart-91026cbb-8d84-4d09-b62d-b61997966fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987829103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2987829103
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1270206010
Short name T267
Test name
Test status
Simulation time 79687464 ps
CPU time 0.74 seconds
Started Jul 19 04:44:34 PM PDT 24
Finished Jul 19 04:44:42 PM PDT 24
Peak memory 194976 kb
Host smart-98433852-e938-4450-bce6-9ec333cae242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270206010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1270206010
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2712720106
Short name T426
Test name
Test status
Simulation time 415204374 ps
CPU time 18.96 seconds
Started Jul 19 04:44:31 PM PDT 24
Finished Jul 19 04:44:57 PM PDT 24
Peak memory 197156 kb
Host smart-f1707c43-772b-4353-8242-0954f0823499
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712720106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2712720106
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1994080268
Short name T242
Test name
Test status
Simulation time 143627613 ps
CPU time 1 seconds
Started Jul 19 04:44:33 PM PDT 24
Finished Jul 19 04:44:41 PM PDT 24
Peak memory 198040 kb
Host smart-336d7e39-7e65-4eb3-996b-e5f3c165b624
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994080268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1994080268
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.919775628
Short name T483
Test name
Test status
Simulation time 177384080 ps
CPU time 1.2 seconds
Started Jul 19 04:44:32 PM PDT 24
Finished Jul 19 04:44:40 PM PDT 24
Peak memory 197544 kb
Host smart-8bbe99ea-b39a-4ca3-9a74-9b484413503c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919775628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.919775628
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.4035544888
Short name T659
Test name
Test status
Simulation time 89904960 ps
CPU time 1.06 seconds
Started Jul 19 04:44:24 PM PDT 24
Finished Jul 19 04:44:29 PM PDT 24
Peak memory 197216 kb
Host smart-255faedf-a411-48af-b96e-5197a2ceef5a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035544888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.4035544888
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3657482035
Short name T613
Test name
Test status
Simulation time 216983939 ps
CPU time 1.27 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:35 PM PDT 24
Peak memory 196744 kb
Host smart-14aa608c-715f-4ea1-bcb5-96adfb6af922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657482035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3657482035
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3408323013
Short name T480
Test name
Test status
Simulation time 24223920 ps
CPU time 0.77 seconds
Started Jul 19 04:44:32 PM PDT 24
Finished Jul 19 04:44:40 PM PDT 24
Peak memory 195400 kb
Host smart-acdcf388-daad-45ff-aa4f-d078f7cbb60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408323013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3408323013
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3368990946
Short name T317
Test name
Test status
Simulation time 51580657 ps
CPU time 1.02 seconds
Started Jul 19 04:44:25 PM PDT 24
Finished Jul 19 04:44:30 PM PDT 24
Peak memory 196188 kb
Host smart-14914000-4bbc-4f7c-9af3-a3da7620e77b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368990946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3368990946
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1526389136
Short name T184
Test name
Test status
Simulation time 129764637 ps
CPU time 1.95 seconds
Started Jul 19 04:44:34 PM PDT 24
Finished Jul 19 04:44:43 PM PDT 24
Peak memory 198244 kb
Host smart-907dc77e-4c5a-445f-98ea-b0fafa9da112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526389136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1526389136
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1939344277
Short name T379
Test name
Test status
Simulation time 143457323 ps
CPU time 1.36 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:39 PM PDT 24
Peak memory 196480 kb
Host smart-65742230-6a4b-4f6c-a6b3-0c04f977a83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939344277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1939344277
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3807308956
Short name T246
Test name
Test status
Simulation time 59345394 ps
CPU time 1.04 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 04:44:33 PM PDT 24
Peak memory 196632 kb
Host smart-967c7662-c128-4d6f-acf7-8fad1f66d2b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807308956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3807308956
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1711784987
Short name T450
Test name
Test status
Simulation time 7352124005 ps
CPU time 188.16 seconds
Started Jul 19 04:44:33 PM PDT 24
Finished Jul 19 04:47:48 PM PDT 24
Peak memory 198332 kb
Host smart-a0655a87-bbdf-467c-a3dd-a9e3ae28fc66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711784987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1711784987
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1365554930
Short name T34
Test name
Test status
Simulation time 47188442061 ps
CPU time 302.21 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:49:35 PM PDT 24
Peak memory 198492 kb
Host smart-27e7c0f0-d08e-4d1d-8c1b-72b73bd9ee80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1365554930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1365554930
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.4004325950
Short name T190
Test name
Test status
Simulation time 14111150 ps
CPU time 0.58 seconds
Started Jul 19 04:44:42 PM PDT 24
Finished Jul 19 04:44:47 PM PDT 24
Peak memory 194900 kb
Host smart-ae91f643-6025-40d1-9cb2-03ca8a1b89fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004325950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.4004325950
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1184282130
Short name T560
Test name
Test status
Simulation time 24190303 ps
CPU time 0.82 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 196144 kb
Host smart-42dd66da-a402-460e-a6b8-52e91fc25398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184282130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1184282130
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.4093265849
Short name T171
Test name
Test status
Simulation time 399157725 ps
CPU time 13.71 seconds
Started Jul 19 04:44:36 PM PDT 24
Finished Jul 19 04:44:56 PM PDT 24
Peak memory 197024 kb
Host smart-2bb9ecc2-cdc9-4e8e-9743-e506e587406e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093265849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.4093265849
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3801437153
Short name T675
Test name
Test status
Simulation time 220216785 ps
CPU time 0.87 seconds
Started Jul 19 04:44:45 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 198048 kb
Host smart-404421f4-04ab-4a83-ac43-4a77549bfdf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801437153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3801437153
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1366026676
Short name T350
Test name
Test status
Simulation time 192213057 ps
CPU time 0.88 seconds
Started Jul 19 04:44:44 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 196708 kb
Host smart-07079e23-e7cb-4949-997f-5af2f8449df0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366026676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1366026676
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3059451143
Short name T622
Test name
Test status
Simulation time 146826237 ps
CPU time 2.27 seconds
Started Jul 19 04:44:27 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 198344 kb
Host smart-69a44fb7-adc3-471f-8b65-513b01053bcb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059451143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3059451143
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3471477093
Short name T55
Test name
Test status
Simulation time 310200793 ps
CPU time 2.48 seconds
Started Jul 19 04:44:46 PM PDT 24
Finished Jul 19 04:44:53 PM PDT 24
Peak memory 197392 kb
Host smart-65004a0e-0565-4a6d-897e-9eec74d01709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471477093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3471477093
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1972652767
Short name T263
Test name
Test status
Simulation time 45709341 ps
CPU time 1.05 seconds
Started Jul 19 04:44:23 PM PDT 24
Finished Jul 19 04:44:27 PM PDT 24
Peak memory 197036 kb
Host smart-82ff49e0-2053-4fdd-8f59-a4ce33259bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972652767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1972652767
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3587320806
Short name T72
Test name
Test status
Simulation time 61207020 ps
CPU time 1.08 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 196296 kb
Host smart-0d6865c7-3aa8-4f5c-b671-3ad6ac819e36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587320806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3587320806
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2913935727
Short name T281
Test name
Test status
Simulation time 281249494 ps
CPU time 3.22 seconds
Started Jul 19 04:44:42 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 198184 kb
Host smart-46c0958c-d048-4e88-870a-168ed4739a17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913935727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2913935727
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1010699353
Short name T534
Test name
Test status
Simulation time 467457030 ps
CPU time 1.24 seconds
Started Jul 19 04:44:28 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 196860 kb
Host smart-a2cb53ae-e9aa-49b1-a681-6ea983a1d613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010699353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1010699353
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.4155831396
Short name T68
Test name
Test status
Simulation time 78290671 ps
CPU time 0.89 seconds
Started Jul 19 04:44:41 PM PDT 24
Finished Jul 19 04:44:47 PM PDT 24
Peak memory 196636 kb
Host smart-6b4ecf3d-6806-4f6d-b22d-2bc7d786896d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155831396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.4155831396
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_alert_test.374673862
Short name T142
Test name
Test status
Simulation time 26117183 ps
CPU time 0.58 seconds
Started Jul 19 04:43:19 PM PDT 24
Finished Jul 19 04:43:22 PM PDT 24
Peak memory 195096 kb
Host smart-e44e75e1-8528-423c-ba2f-646e0093addf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374673862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.374673862
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.148049203
Short name T533
Test name
Test status
Simulation time 169735329 ps
CPU time 0.84 seconds
Started Jul 19 04:43:17 PM PDT 24
Finished Jul 19 04:43:20 PM PDT 24
Peak memory 196780 kb
Host smart-54ae1d68-0ccf-4692-8c9b-f82e7bff72dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148049203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.148049203
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.142684449
Short name T408
Test name
Test status
Simulation time 522809661 ps
CPU time 2.91 seconds
Started Jul 19 04:43:21 PM PDT 24
Finished Jul 19 04:43:26 PM PDT 24
Peak memory 196064 kb
Host smart-e71607ca-d299-4a4e-9a38-122aad67e4b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142684449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.142684449
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2104887205
Short name T465
Test name
Test status
Simulation time 162757404 ps
CPU time 0.85 seconds
Started Jul 19 04:43:27 PM PDT 24
Finished Jul 19 04:43:34 PM PDT 24
Peak memory 196252 kb
Host smart-90a9d294-c4cf-4305-8551-c0d64434996f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104887205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2104887205
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2911824529
Short name T292
Test name
Test status
Simulation time 39131034 ps
CPU time 1.1 seconds
Started Jul 19 04:43:15 PM PDT 24
Finished Jul 19 04:43:19 PM PDT 24
Peak memory 196872 kb
Host smart-518a5911-290b-4a44-8d28-ce170c3b284f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911824529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2911824529
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.139756032
Short name T535
Test name
Test status
Simulation time 34857147 ps
CPU time 1.32 seconds
Started Jul 19 04:43:25 PM PDT 24
Finished Jul 19 04:43:30 PM PDT 24
Peak memory 196748 kb
Host smart-47deecc8-9811-40a7-b493-97d3d3f22865
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139756032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.139756032
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3658357070
Short name T178
Test name
Test status
Simulation time 849531785 ps
CPU time 2.87 seconds
Started Jul 19 04:43:16 PM PDT 24
Finished Jul 19 04:43:21 PM PDT 24
Peak memory 197408 kb
Host smart-42e41905-41e8-426f-9f2a-b38be0d0bdc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658357070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3658357070
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2523988237
Short name T701
Test name
Test status
Simulation time 68394635 ps
CPU time 1.28 seconds
Started Jul 19 04:43:18 PM PDT 24
Finished Jul 19 04:43:22 PM PDT 24
Peak memory 198320 kb
Host smart-48fd5764-5cf2-4897-8483-0fb095974e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523988237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2523988237
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3192790748
Short name T468
Test name
Test status
Simulation time 18208626 ps
CPU time 0.67 seconds
Started Jul 19 04:43:19 PM PDT 24
Finished Jul 19 04:43:22 PM PDT 24
Peak memory 195180 kb
Host smart-a5ff2ae0-2611-458c-acbd-aaec4ecbb0e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192790748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3192790748
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3343303454
Short name T2
Test name
Test status
Simulation time 1523706270 ps
CPU time 3.57 seconds
Started Jul 19 04:43:16 PM PDT 24
Finished Jul 19 04:43:21 PM PDT 24
Peak memory 198352 kb
Host smart-736a6da7-8fc0-4597-b5f2-1ecf477db962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343303454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3343303454
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2999899845
Short name T42
Test name
Test status
Simulation time 139099239 ps
CPU time 0.78 seconds
Started Jul 19 04:43:16 PM PDT 24
Finished Jul 19 04:43:19 PM PDT 24
Peak memory 214164 kb
Host smart-e3b02f31-cb85-48a9-9112-263b804768ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999899845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2999899845
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3389368773
Short name T196
Test name
Test status
Simulation time 67994188 ps
CPU time 1.19 seconds
Started Jul 19 04:43:27 PM PDT 24
Finished Jul 19 04:43:33 PM PDT 24
Peak memory 196068 kb
Host smart-025ed159-5ae6-44d2-b77f-4fe0f12795c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389368773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3389368773
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.895421972
Short name T663
Test name
Test status
Simulation time 401061089 ps
CPU time 1.41 seconds
Started Jul 19 04:43:19 PM PDT 24
Finished Jul 19 04:43:23 PM PDT 24
Peak memory 196996 kb
Host smart-801cf59c-2019-4244-a803-4190575fd68f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895421972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.895421972
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1218521701
Short name T255
Test name
Test status
Simulation time 7498693928 ps
CPU time 45.26 seconds
Started Jul 19 04:43:20 PM PDT 24
Finished Jul 19 04:44:08 PM PDT 24
Peak memory 198116 kb
Host smart-cc4d4968-472a-421a-a392-f9c003e1e171
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218521701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1218521701
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.4226510579
Short name T536
Test name
Test status
Simulation time 44685089204 ps
CPU time 851.01 seconds
Started Jul 19 04:43:16 PM PDT 24
Finished Jul 19 04:57:30 PM PDT 24
Peak memory 198412 kb
Host smart-7beee416-6b23-4c90-8fc4-d1ac73fc9c54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4226510579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.4226510579
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.4032247287
Short name T98
Test name
Test status
Simulation time 16554052 ps
CPU time 0.56 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:38 PM PDT 24
Peak memory 194404 kb
Host smart-69d7e53a-fbde-4521-a989-2ccdfc558078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032247287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.4032247287
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3544050333
Short name T434
Test name
Test status
Simulation time 45630572 ps
CPU time 0.83 seconds
Started Jul 19 04:44:37 PM PDT 24
Finished Jul 19 04:44:43 PM PDT 24
Peak memory 195024 kb
Host smart-5f7096e2-dec9-44ca-819b-6615f6056a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544050333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3544050333
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.669858847
Short name T53
Test name
Test status
Simulation time 5281277943 ps
CPU time 16.57 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:53 PM PDT 24
Peak memory 198316 kb
Host smart-9cf83af7-3960-4228-a35e-c525f8f21875
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669858847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.669858847
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2977501558
Short name T592
Test name
Test status
Simulation time 54002264 ps
CPU time 0.88 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 196992 kb
Host smart-bb31bba6-70ce-4960-a7f6-42ce4918e7b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977501558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2977501558
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.971354745
Short name T575
Test name
Test status
Simulation time 159127386 ps
CPU time 1.05 seconds
Started Jul 19 04:44:37 PM PDT 24
Finished Jul 19 04:44:43 PM PDT 24
Peak memory 196844 kb
Host smart-5bc73649-7a58-42e7-abd6-1faf67fcd3e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971354745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.971354745
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.4165839083
Short name T272
Test name
Test status
Simulation time 91686997 ps
CPU time 3.47 seconds
Started Jul 19 04:44:31 PM PDT 24
Finished Jul 19 04:44:41 PM PDT 24
Peak memory 198260 kb
Host smart-16489698-2706-4f37-bf93-afac643be59b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165839083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.4165839083
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3242638453
Short name T660
Test name
Test status
Simulation time 565251168 ps
CPU time 3.02 seconds
Started Jul 19 04:44:39 PM PDT 24
Finished Jul 19 04:44:47 PM PDT 24
Peak memory 197324 kb
Host smart-12f64450-6fae-4f48-afee-631666fb57ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242638453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3242638453
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2207283957
Short name T573
Test name
Test status
Simulation time 35997240 ps
CPU time 1.3 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:37 PM PDT 24
Peak memory 195968 kb
Host smart-c3f283b5-c7dd-4a63-9487-0b20a81584ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207283957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2207283957
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3137149943
Short name T275
Test name
Test status
Simulation time 34559596 ps
CPU time 0.85 seconds
Started Jul 19 04:44:46 PM PDT 24
Finished Jul 19 04:44:51 PM PDT 24
Peak memory 196064 kb
Host smart-b9362328-91cf-4e68-a3f3-e939fa7b4da7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137149943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3137149943
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2145962532
Short name T351
Test name
Test status
Simulation time 444866229 ps
CPU time 5.41 seconds
Started Jul 19 04:44:36 PM PDT 24
Finished Jul 19 04:44:47 PM PDT 24
Peak memory 198192 kb
Host smart-ea762c78-bf83-43f9-84ed-f97afa6b8908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145962532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2145962532
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.267197131
Short name T320
Test name
Test status
Simulation time 437295135 ps
CPU time 0.91 seconds
Started Jul 19 04:44:41 PM PDT 24
Finished Jul 19 04:44:47 PM PDT 24
Peak memory 195792 kb
Host smart-8d019fb2-7b34-4d5f-ba83-b6359f8e408f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267197131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.267197131
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3515046595
Short name T59
Test name
Test status
Simulation time 70154959 ps
CPU time 1.26 seconds
Started Jul 19 04:44:39 PM PDT 24
Finished Jul 19 04:44:45 PM PDT 24
Peak memory 197072 kb
Host smart-7d3e8178-ea03-4728-81c4-2105ea2482fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515046595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3515046595
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1402422409
Short name T159
Test name
Test status
Simulation time 2815301717 ps
CPU time 37.71 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:45:15 PM PDT 24
Peak memory 198344 kb
Host smart-117e57ad-174f-4e9e-ad37-357b3fb3c493
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402422409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1402422409
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2462644505
Short name T633
Test name
Test status
Simulation time 53122731 ps
CPU time 0.61 seconds
Started Jul 19 04:44:46 PM PDT 24
Finished Jul 19 04:44:52 PM PDT 24
Peak memory 194888 kb
Host smart-859ecdeb-d0b3-4086-9ecd-312cf7149221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462644505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2462644505
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3146622112
Short name T598
Test name
Test status
Simulation time 28928350 ps
CPU time 0.8 seconds
Started Jul 19 04:44:31 PM PDT 24
Finished Jul 19 04:44:39 PM PDT 24
Peak memory 195316 kb
Host smart-1cdb928a-1c65-4e37-ad26-f2a03da51e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146622112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3146622112
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1860285593
Short name T78
Test name
Test status
Simulation time 561111326 ps
CPU time 4.36 seconds
Started Jul 19 04:44:43 PM PDT 24
Finished Jul 19 04:44:52 PM PDT 24
Peak memory 195740 kb
Host smart-44e2a825-3a98-47eb-9a11-c6b73e9238d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860285593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1860285593
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1093040586
Short name T362
Test name
Test status
Simulation time 133320581 ps
CPU time 0.71 seconds
Started Jul 19 04:44:31 PM PDT 24
Finished Jul 19 04:44:38 PM PDT 24
Peak memory 194884 kb
Host smart-f1c74b8c-3f53-487e-9f8a-cae5f51abc7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093040586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1093040586
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.280391322
Short name T461
Test name
Test status
Simulation time 74995323 ps
CPU time 1.13 seconds
Started Jul 19 04:44:44 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 196364 kb
Host smart-f580b9c6-32b4-484f-8824-548cdfc93c15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280391322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.280391322
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1788675150
Short name T459
Test name
Test status
Simulation time 156573938 ps
CPU time 1.68 seconds
Started Jul 19 04:44:34 PM PDT 24
Finished Jul 19 04:44:42 PM PDT 24
Peak memory 196672 kb
Host smart-e0face41-4124-4a7a-b3c8-8ea07a24b073
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788675150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1788675150
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2674651468
Short name T167
Test name
Test status
Simulation time 212448504 ps
CPU time 2.52 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:38 PM PDT 24
Peak memory 196708 kb
Host smart-8e7079b1-b9b1-407d-b46a-c6b2ebd49de7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674651468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2674651468
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.939297498
Short name T352
Test name
Test status
Simulation time 182293419 ps
CPU time 1.06 seconds
Started Jul 19 04:44:40 PM PDT 24
Finished Jul 19 04:44:46 PM PDT 24
Peak memory 197004 kb
Host smart-5880ae28-5eb6-4f0b-98e3-07a0041ba950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939297498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.939297498
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2476379225
Short name T656
Test name
Test status
Simulation time 240647016 ps
CPU time 1.24 seconds
Started Jul 19 04:44:31 PM PDT 24
Finished Jul 19 04:44:39 PM PDT 24
Peak memory 198164 kb
Host smart-0448cd40-1afc-4796-9a52-c8e37ba6a8e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476379225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2476379225
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.55886807
Short name T604
Test name
Test status
Simulation time 518233021 ps
CPU time 4.35 seconds
Started Jul 19 04:44:36 PM PDT 24
Finished Jul 19 04:44:46 PM PDT 24
Peak memory 198192 kb
Host smart-43108501-62b2-40e4-b79d-5072bada3a3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55886807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand
om_long_reg_writes_reg_reads.55886807
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.4090282500
Short name T343
Test name
Test status
Simulation time 46923515 ps
CPU time 0.86 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 195576 kb
Host smart-d64d7aab-81d6-4098-a5d9-97e94b5c764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090282500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.4090282500
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3321422531
Short name T503
Test name
Test status
Simulation time 49354980 ps
CPU time 1.31 seconds
Started Jul 19 04:44:43 PM PDT 24
Finished Jul 19 04:44:49 PM PDT 24
Peak memory 197060 kb
Host smart-2b1fe209-449f-467c-b9ba-8242efbb58f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321422531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3321422531
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2904091999
Short name T597
Test name
Test status
Simulation time 8151811803 ps
CPU time 22.58 seconds
Started Jul 19 04:44:29 PM PDT 24
Finished Jul 19 04:44:58 PM PDT 24
Peak memory 198280 kb
Host smart-46f391eb-25ea-47e2-bb2e-41ee70ddf8ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904091999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2904091999
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3831187985
Short name T81
Test name
Test status
Simulation time 611033083808 ps
CPU time 1698.21 seconds
Started Jul 19 04:44:45 PM PDT 24
Finished Jul 19 05:13:08 PM PDT 24
Peak memory 198516 kb
Host smart-67038042-8e83-4330-82b4-f72d15b1715c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3831187985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3831187985
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2404047375
Short name T514
Test name
Test status
Simulation time 30953485 ps
CPU time 0.59 seconds
Started Jul 19 04:44:49 PM PDT 24
Finished Jul 19 04:44:55 PM PDT 24
Peak memory 194344 kb
Host smart-c955ec67-fd26-468d-a254-eca4505730d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404047375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2404047375
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3654672249
Short name T611
Test name
Test status
Simulation time 77901239 ps
CPU time 0.83 seconds
Started Jul 19 04:44:33 PM PDT 24
Finished Jul 19 04:44:41 PM PDT 24
Peak memory 195580 kb
Host smart-6718c9f5-4137-43b4-8e9f-df66be3b28d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654672249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3654672249
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2800744555
Short name T240
Test name
Test status
Simulation time 365830756 ps
CPU time 18.95 seconds
Started Jul 19 04:44:30 PM PDT 24
Finished Jul 19 04:44:56 PM PDT 24
Peak memory 197160 kb
Host smart-166ed148-5cd8-418b-b130-fea20399da55
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800744555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2800744555
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2976680115
Short name T499
Test name
Test status
Simulation time 52942062 ps
CPU time 0.65 seconds
Started Jul 19 04:44:45 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 194792 kb
Host smart-5ff8ebe1-20a4-438b-a18a-0578b44494f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976680115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2976680115
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.338281912
Short name T324
Test name
Test status
Simulation time 64676341 ps
CPU time 0.82 seconds
Started Jul 19 04:44:45 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 196504 kb
Host smart-24851568-30f8-4acf-b543-3a846dc0ada5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338281912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.338281912
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3055278360
Short name T156
Test name
Test status
Simulation time 72450960 ps
CPU time 1.66 seconds
Started Jul 19 04:44:44 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 195996 kb
Host smart-83be17cc-575a-4b2f-83c2-69069a99a3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055278360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3055278360
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1661211279
Short name T331
Test name
Test status
Simulation time 31995642 ps
CPU time 1.06 seconds
Started Jul 19 04:44:43 PM PDT 24
Finished Jul 19 04:44:49 PM PDT 24
Peak memory 196352 kb
Host smart-8f028407-f421-4f3b-b52d-163ad7bf89c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661211279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1661211279
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2000405772
Short name T481
Test name
Test status
Simulation time 59990290 ps
CPU time 1.18 seconds
Started Jul 19 04:44:35 PM PDT 24
Finished Jul 19 04:44:43 PM PDT 24
Peak memory 197280 kb
Host smart-81240e8b-3b49-476f-9c45-52f928b69ef4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000405772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2000405772
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1624382158
Short name T319
Test name
Test status
Simulation time 119730324 ps
CPU time 5.39 seconds
Started Jul 19 04:44:44 PM PDT 24
Finished Jul 19 04:44:54 PM PDT 24
Peak memory 198148 kb
Host smart-a43449ea-f6ce-411f-874e-bd23b105309c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624382158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1624382158
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2371632413
Short name T678
Test name
Test status
Simulation time 63331608 ps
CPU time 1.39 seconds
Started Jul 19 04:44:37 PM PDT 24
Finished Jul 19 04:44:44 PM PDT 24
Peak memory 196984 kb
Host smart-c2702024-ffb7-4ac2-8f47-5f5c21639dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371632413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2371632413
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1119428956
Short name T228
Test name
Test status
Simulation time 64020385 ps
CPU time 1.07 seconds
Started Jul 19 04:44:33 PM PDT 24
Finished Jul 19 04:44:41 PM PDT 24
Peak memory 195988 kb
Host smart-94a02a73-851b-4189-9ef9-29dbe9c6c1ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119428956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1119428956
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3535514272
Short name T692
Test name
Test status
Simulation time 9237418914 ps
CPU time 155.62 seconds
Started Jul 19 04:44:46 PM PDT 24
Finished Jul 19 04:47:26 PM PDT 24
Peak memory 198296 kb
Host smart-a29af687-febb-49c3-8cc0-29ef55eff89e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535514272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3535514272
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.4013159507
Short name T609
Test name
Test status
Simulation time 61087434720 ps
CPU time 732.24 seconds
Started Jul 19 04:44:47 PM PDT 24
Finished Jul 19 04:57:04 PM PDT 24
Peak memory 198484 kb
Host smart-d8829783-d4ec-416d-acad-3998035619ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4013159507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.4013159507
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3449777752
Short name T283
Test name
Test status
Simulation time 30667581 ps
CPU time 0.57 seconds
Started Jul 19 04:44:49 PM PDT 24
Finished Jul 19 04:44:55 PM PDT 24
Peak memory 194084 kb
Host smart-525c8374-9b64-4e05-9e86-20ec25f7a097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449777752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3449777752
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4063991522
Short name T186
Test name
Test status
Simulation time 97083192 ps
CPU time 0.96 seconds
Started Jul 19 04:44:44 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 196172 kb
Host smart-f088685d-fa4b-4c02-a1ac-2415c1ba5436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063991522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4063991522
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1868733934
Short name T203
Test name
Test status
Simulation time 1533145882 ps
CPU time 9.94 seconds
Started Jul 19 04:44:55 PM PDT 24
Finished Jul 19 04:45:10 PM PDT 24
Peak memory 198192 kb
Host smart-3daa8637-b157-4d15-ac9f-efb474b95cdd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868733934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1868733934
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3841446468
Short name T118
Test name
Test status
Simulation time 192398014 ps
CPU time 0.94 seconds
Started Jul 19 04:44:43 PM PDT 24
Finished Jul 19 04:44:49 PM PDT 24
Peak memory 197320 kb
Host smart-840e6462-aa35-493d-bad7-3549bbd56d05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841446468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3841446468
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2663929301
Short name T96
Test name
Test status
Simulation time 41759823 ps
CPU time 0.9 seconds
Started Jul 19 04:44:49 PM PDT 24
Finished Jul 19 04:44:54 PM PDT 24
Peak memory 196628 kb
Host smart-ef3222eb-cfbf-4ed0-885d-527f6028aab1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663929301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2663929301
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3466109690
Short name T431
Test name
Test status
Simulation time 161846267 ps
CPU time 3.18 seconds
Started Jul 19 04:44:44 PM PDT 24
Finished Jul 19 04:44:52 PM PDT 24
Peak memory 198312 kb
Host smart-86fce988-fceb-4e4d-8b16-3701e73da389
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466109690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3466109690
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1961229077
Short name T655
Test name
Test status
Simulation time 58578411 ps
CPU time 1.63 seconds
Started Jul 19 04:44:55 PM PDT 24
Finished Jul 19 04:45:01 PM PDT 24
Peak memory 196788 kb
Host smart-e1f5153d-704a-4982-bf9b-e740b19a3de1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961229077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1961229077
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.644507904
Short name T511
Test name
Test status
Simulation time 63830385 ps
CPU time 1.24 seconds
Started Jul 19 04:44:41 PM PDT 24
Finished Jul 19 04:44:47 PM PDT 24
Peak memory 197200 kb
Host smart-aee2df7e-1419-4307-aaac-a4471f8e8c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644507904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.644507904
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1116796940
Short name T134
Test name
Test status
Simulation time 49129248 ps
CPU time 0.75 seconds
Started Jul 19 04:44:46 PM PDT 24
Finished Jul 19 04:44:51 PM PDT 24
Peak memory 195564 kb
Host smart-a012dd35-d571-4893-bbdb-4d689440e17e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116796940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1116796940
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2681475152
Short name T443
Test name
Test status
Simulation time 260988286 ps
CPU time 4.14 seconds
Started Jul 19 04:44:43 PM PDT 24
Finished Jul 19 04:44:52 PM PDT 24
Peak memory 198188 kb
Host smart-f205747a-7230-4f29-bb5c-047f8123ec47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681475152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2681475152
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3906360248
Short name T641
Test name
Test status
Simulation time 121629666 ps
CPU time 0.99 seconds
Started Jul 19 04:44:47 PM PDT 24
Finished Jul 19 04:44:54 PM PDT 24
Peak memory 195740 kb
Host smart-bf619bd6-b2c9-4e63-a629-4ee7784de8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906360248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3906360248
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.69351394
Short name T547
Test name
Test status
Simulation time 128175945 ps
CPU time 1.09 seconds
Started Jul 19 04:44:49 PM PDT 24
Finished Jul 19 04:44:54 PM PDT 24
Peak memory 195984 kb
Host smart-3510b674-2626-4d6e-902c-a0c315832a90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69351394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.69351394
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.4222115957
Short name T651
Test name
Test status
Simulation time 39486099492 ps
CPU time 157.48 seconds
Started Jul 19 04:44:42 PM PDT 24
Finished Jul 19 04:47:24 PM PDT 24
Peak memory 198268 kb
Host smart-89a1507d-e84d-4863-9acf-c2e60338c9e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222115957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.4222115957
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1862288252
Short name T627
Test name
Test status
Simulation time 21757247 ps
CPU time 0.57 seconds
Started Jul 19 04:44:48 PM PDT 24
Finished Jul 19 04:44:54 PM PDT 24
Peak memory 194188 kb
Host smart-372563e2-cbf8-4b5f-9c99-ba0db04f3261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862288252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1862288252
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3372748651
Short name T222
Test name
Test status
Simulation time 122804168 ps
CPU time 0.84 seconds
Started Jul 19 04:45:01 PM PDT 24
Finished Jul 19 04:45:07 PM PDT 24
Peak memory 196632 kb
Host smart-96d3a519-9879-447b-b38f-b0fc02db0483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372748651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3372748651
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3810488388
Short name T309
Test name
Test status
Simulation time 449985607 ps
CPU time 14.11 seconds
Started Jul 19 04:44:41 PM PDT 24
Finished Jul 19 04:45:00 PM PDT 24
Peak memory 198292 kb
Host smart-d1e880a0-a5b0-45d2-880d-482b040d75c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810488388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3810488388
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3832046029
Short name T300
Test name
Test status
Simulation time 91038938 ps
CPU time 0.66 seconds
Started Jul 19 04:44:45 PM PDT 24
Finished Jul 19 04:44:51 PM PDT 24
Peak memory 194888 kb
Host smart-c81610d8-5bdc-417a-89ec-95725d3c5079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832046029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3832046029
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.597525107
Short name T143
Test name
Test status
Simulation time 30375433 ps
CPU time 0.96 seconds
Started Jul 19 04:44:44 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 196304 kb
Host smart-0ec498fa-48bb-45a1-952d-c3afad52a221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597525107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.597525107
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2225692616
Short name T702
Test name
Test status
Simulation time 103830294 ps
CPU time 3.65 seconds
Started Jul 19 04:44:42 PM PDT 24
Finished Jul 19 04:44:51 PM PDT 24
Peak memory 198252 kb
Host smart-f0446c9c-9b29-4452-aff9-0b1f48a0792a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225692616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2225692616
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1908052233
Short name T591
Test name
Test status
Simulation time 420364186 ps
CPU time 3.05 seconds
Started Jul 19 04:44:41 PM PDT 24
Finished Jul 19 04:44:49 PM PDT 24
Peak memory 197332 kb
Host smart-ccb6bbc4-a317-4043-ad46-5827b664e5a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908052233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1908052233
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3649158968
Short name T488
Test name
Test status
Simulation time 64715560 ps
CPU time 1.2 seconds
Started Jul 19 04:44:47 PM PDT 24
Finished Jul 19 04:44:53 PM PDT 24
Peak memory 198292 kb
Host smart-8ae71b6a-ccfa-46e8-bf00-f66ad1e8df3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649158968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3649158968
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2775143034
Short name T365
Test name
Test status
Simulation time 72646700 ps
CPU time 1.03 seconds
Started Jul 19 04:44:49 PM PDT 24
Finished Jul 19 04:44:54 PM PDT 24
Peak memory 196104 kb
Host smart-a8826092-7b53-4b95-aa45-16eb52b84062
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775143034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2775143034
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.675275738
Short name T484
Test name
Test status
Simulation time 442624377 ps
CPU time 5.19 seconds
Started Jul 19 04:44:42 PM PDT 24
Finished Jul 19 04:44:53 PM PDT 24
Peak memory 198104 kb
Host smart-714b92c1-d233-46e3-9aee-c780ddbff602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675275738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.675275738
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.425705876
Short name T694
Test name
Test status
Simulation time 45000026 ps
CPU time 1.04 seconds
Started Jul 19 04:44:49 PM PDT 24
Finished Jul 19 04:44:55 PM PDT 24
Peak memory 195900 kb
Host smart-92f9588b-dd12-4203-a36b-ee828215c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425705876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.425705876
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3071080933
Short name T631
Test name
Test status
Simulation time 281846070 ps
CPU time 1.09 seconds
Started Jul 19 04:44:47 PM PDT 24
Finished Jul 19 04:44:53 PM PDT 24
Peak memory 196488 kb
Host smart-1e79d6f8-d374-469d-95a3-94355dfe27d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071080933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3071080933
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1613268503
Short name T685
Test name
Test status
Simulation time 3574050957 ps
CPU time 97.55 seconds
Started Jul 19 04:44:45 PM PDT 24
Finished Jul 19 04:46:27 PM PDT 24
Peak memory 198336 kb
Host smart-7149be44-d758-46bc-9cef-a08fb36411cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613268503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1613268503
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2454610047
Short name T496
Test name
Test status
Simulation time 44306335 ps
CPU time 0.56 seconds
Started Jul 19 04:44:56 PM PDT 24
Finished Jul 19 04:45:01 PM PDT 24
Peak memory 194884 kb
Host smart-cc007c52-a6ed-426f-96aa-4c4084f0aeb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454610047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2454610047
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3390149085
Short name T342
Test name
Test status
Simulation time 31081964 ps
CPU time 0.75 seconds
Started Jul 19 04:44:42 PM PDT 24
Finished Jul 19 04:44:48 PM PDT 24
Peak memory 195344 kb
Host smart-21e136cd-ef3f-4f9b-bf3e-20701e60522f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390149085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3390149085
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1653502603
Short name T221
Test name
Test status
Simulation time 713628439 ps
CPU time 22.91 seconds
Started Jul 19 04:44:42 PM PDT 24
Finished Jul 19 04:45:10 PM PDT 24
Peak memory 197096 kb
Host smart-e01826c1-575b-4fbe-8e18-ce2b226ddf07
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653502603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1653502603
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.418446895
Short name T637
Test name
Test status
Simulation time 196827152 ps
CPU time 1.1 seconds
Started Jul 19 04:44:44 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 196832 kb
Host smart-12fa38bc-600b-4db3-97db-df959e731863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418446895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.418446895
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2990165921
Short name T400
Test name
Test status
Simulation time 176348524 ps
CPU time 1.16 seconds
Started Jul 19 04:44:44 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 196140 kb
Host smart-fbfc88d4-0199-49e4-a0a9-66a7c4787128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990165921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2990165921
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2583279595
Short name T274
Test name
Test status
Simulation time 187491541 ps
CPU time 3.4 seconds
Started Jul 19 04:44:47 PM PDT 24
Finished Jul 19 04:44:55 PM PDT 24
Peak memory 198260 kb
Host smart-3672f266-35e0-485e-a99f-2d991d4d5705
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583279595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2583279595
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2001406497
Short name T428
Test name
Test status
Simulation time 233378905 ps
CPU time 3.48 seconds
Started Jul 19 04:44:46 PM PDT 24
Finished Jul 19 04:44:54 PM PDT 24
Peak memory 196760 kb
Host smart-3ca1d2af-0668-438c-8ea0-6ca9ef690771
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001406497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2001406497
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.207039027
Short name T569
Test name
Test status
Simulation time 172454471 ps
CPU time 1.1 seconds
Started Jul 19 04:44:52 PM PDT 24
Finished Jul 19 04:44:58 PM PDT 24
Peak memory 196124 kb
Host smart-bfc3ea4c-dcdc-4c7b-b689-da6808416399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207039027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.207039027
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3916623084
Short name T664
Test name
Test status
Simulation time 108288939 ps
CPU time 1.13 seconds
Started Jul 19 04:44:46 PM PDT 24
Finished Jul 19 04:44:52 PM PDT 24
Peak memory 197288 kb
Host smart-1b66bcfc-d23e-4c10-8881-406fff3006ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916623084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3916623084
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.795554495
Short name T359
Test name
Test status
Simulation time 368696531 ps
CPU time 1.66 seconds
Started Jul 19 04:44:45 PM PDT 24
Finished Jul 19 04:44:52 PM PDT 24
Peak memory 198208 kb
Host smart-a9afc637-a4e7-4c62-b779-a8a35e4f50b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795554495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.795554495
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2482222320
Short name T494
Test name
Test status
Simulation time 103614551 ps
CPU time 0.96 seconds
Started Jul 19 04:44:49 PM PDT 24
Finished Jul 19 04:44:55 PM PDT 24
Peak memory 195916 kb
Host smart-81007597-8463-4235-bb2c-ad4f1d7f1a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482222320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2482222320
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3158808799
Short name T485
Test name
Test status
Simulation time 164128687 ps
CPU time 0.95 seconds
Started Jul 19 04:44:43 PM PDT 24
Finished Jul 19 04:44:49 PM PDT 24
Peak memory 197172 kb
Host smart-3979e441-66e2-4447-af25-eccea4814124
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158808799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3158808799
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3321401147
Short name T11
Test name
Test status
Simulation time 23136984107 ps
CPU time 142.16 seconds
Started Jul 19 04:44:45 PM PDT 24
Finished Jul 19 04:47:12 PM PDT 24
Peak memory 198328 kb
Host smart-0344ccc4-aa90-402a-9515-829b001dd4fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321401147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3321401147
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2578963787
Short name T489
Test name
Test status
Simulation time 11266508 ps
CPU time 0.57 seconds
Started Jul 19 04:44:53 PM PDT 24
Finished Jul 19 04:44:58 PM PDT 24
Peak memory 194120 kb
Host smart-da3940b9-57e3-4c87-a4b9-810de38b5ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578963787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2578963787
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3515186185
Short name T653
Test name
Test status
Simulation time 43360404 ps
CPU time 0.72 seconds
Started Jul 19 04:45:03 PM PDT 24
Finished Jul 19 04:45:08 PM PDT 24
Peak memory 195072 kb
Host smart-ba0c462c-5133-4b37-8518-a994ce685fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515186185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3515186185
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1619030452
Short name T173
Test name
Test status
Simulation time 613056307 ps
CPU time 25.45 seconds
Started Jul 19 04:44:53 PM PDT 24
Finished Jul 19 04:45:23 PM PDT 24
Peak memory 197084 kb
Host smart-4a1b9315-e9a9-4ae5-a7f7-d72020933a05
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619030452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1619030452
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1909881045
Short name T278
Test name
Test status
Simulation time 281696441 ps
CPU time 0.95 seconds
Started Jul 19 04:45:01 PM PDT 24
Finished Jul 19 04:45:07 PM PDT 24
Peak memory 196904 kb
Host smart-b310e14f-a0f6-4032-8c6f-f8d925c51027
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909881045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1909881045
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.900697998
Short name T298
Test name
Test status
Simulation time 72722160 ps
CPU time 1.26 seconds
Started Jul 19 04:44:54 PM PDT 24
Finished Jul 19 04:45:00 PM PDT 24
Peak memory 196268 kb
Host smart-54cce45c-d4ea-497b-88e4-f89817fff93b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900697998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.900697998
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.356371079
Short name T250
Test name
Test status
Simulation time 52366495 ps
CPU time 1.25 seconds
Started Jul 19 04:45:06 PM PDT 24
Finished Jul 19 04:45:11 PM PDT 24
Peak memory 198352 kb
Host smart-c674556b-3337-4985-9979-e09329f7d006
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356371079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.356371079
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.872229497
Short name T306
Test name
Test status
Simulation time 1614385022 ps
CPU time 3.34 seconds
Started Jul 19 04:44:54 PM PDT 24
Finished Jul 19 04:45:02 PM PDT 24
Peak memory 197280 kb
Host smart-c43a92f7-80ae-4228-8024-765714656b14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872229497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
872229497
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1853925856
Short name T572
Test name
Test status
Simulation time 24023342 ps
CPU time 0.76 seconds
Started Jul 19 04:44:56 PM PDT 24
Finished Jul 19 04:45:01 PM PDT 24
Peak memory 195580 kb
Host smart-7e04b806-3565-4b38-b250-5a26e82bc0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853925856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1853925856
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.816361039
Short name T13
Test name
Test status
Simulation time 20289937 ps
CPU time 0.77 seconds
Started Jul 19 04:45:02 PM PDT 24
Finished Jul 19 04:45:08 PM PDT 24
Peak memory 195760 kb
Host smart-d5247b5d-b563-46b8-bc4a-0f08759390f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816361039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.816361039
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.905925296
Short name T411
Test name
Test status
Simulation time 2157080506 ps
CPU time 6.69 seconds
Started Jul 19 04:44:54 PM PDT 24
Finished Jul 19 04:45:05 PM PDT 24
Peak memory 197860 kb
Host smart-724edefb-8ee5-4387-9b79-73c912c261b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905925296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.905925296
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.507315214
Short name T650
Test name
Test status
Simulation time 39925041 ps
CPU time 1.05 seconds
Started Jul 19 04:44:51 PM PDT 24
Finished Jul 19 04:44:57 PM PDT 24
Peak memory 195928 kb
Host smart-daf074ff-dafa-4ada-8719-0985595e2865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507315214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.507315214
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.178969959
Short name T293
Test name
Test status
Simulation time 150412362 ps
CPU time 0.92 seconds
Started Jul 19 04:44:59 PM PDT 24
Finished Jul 19 04:45:05 PM PDT 24
Peak memory 195764 kb
Host smart-74a55cf4-eb83-43eb-a160-86ecc9f83cf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178969959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.178969959
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2640726141
Short name T448
Test name
Test status
Simulation time 113329689871 ps
CPU time 179.98 seconds
Started Jul 19 04:44:54 PM PDT 24
Finished Jul 19 04:47:58 PM PDT 24
Peak memory 198212 kb
Host smart-fd419f27-32f4-4b41-9fb5-fcf2e5e660a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640726141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2640726141
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2548083043
Short name T97
Test name
Test status
Simulation time 46314272 ps
CPU time 0.54 seconds
Started Jul 19 04:44:55 PM PDT 24
Finished Jul 19 04:45:00 PM PDT 24
Peak memory 193660 kb
Host smart-b4c35c66-1bd5-46f2-ba10-b4ce3028cc3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548083043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2548083043
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2800763256
Short name T277
Test name
Test status
Simulation time 111393665 ps
CPU time 0.72 seconds
Started Jul 19 04:44:50 PM PDT 24
Finished Jul 19 04:44:56 PM PDT 24
Peak memory 195412 kb
Host smart-bf3641b4-0547-4b58-98e1-4969ed53ec31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800763256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2800763256
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1651578148
Short name T424
Test name
Test status
Simulation time 864237628 ps
CPU time 21.94 seconds
Started Jul 19 04:44:53 PM PDT 24
Finished Jul 19 04:45:19 PM PDT 24
Peak memory 198224 kb
Host smart-e4d35d2a-de01-4261-bc03-09a1e1b2776c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651578148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1651578148
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3834634811
Short name T558
Test name
Test status
Simulation time 84416162 ps
CPU time 0.9 seconds
Started Jul 19 04:44:54 PM PDT 24
Finished Jul 19 04:45:00 PM PDT 24
Peak memory 197104 kb
Host smart-3d472d58-dfdf-4909-a80d-836d63d43d2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834634811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3834634811
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3225314732
Short name T200
Test name
Test status
Simulation time 32933408 ps
CPU time 0.74 seconds
Started Jul 19 04:44:55 PM PDT 24
Finished Jul 19 04:45:00 PM PDT 24
Peak memory 195616 kb
Host smart-4aad1638-7fc0-4275-9955-125d8f955d1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225314732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3225314732
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2721313996
Short name T586
Test name
Test status
Simulation time 47093247 ps
CPU time 1.92 seconds
Started Jul 19 04:44:56 PM PDT 24
Finished Jul 19 04:45:04 PM PDT 24
Peak memory 196480 kb
Host smart-87db8c1e-f78e-4d4b-9699-42f38581e412
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721313996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2721313996
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2169556141
Short name T212
Test name
Test status
Simulation time 198873067 ps
CPU time 2.17 seconds
Started Jul 19 04:44:54 PM PDT 24
Finished Jul 19 04:45:01 PM PDT 24
Peak memory 196740 kb
Host smart-aba86196-af91-47fe-9bc5-683a24a19ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169556141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2169556141
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3621399401
Short name T368
Test name
Test status
Simulation time 50955411 ps
CPU time 1.04 seconds
Started Jul 19 04:44:51 PM PDT 24
Finished Jul 19 04:44:57 PM PDT 24
Peak memory 196280 kb
Host smart-9f62b87b-c00a-4f31-8738-ab3d2821b50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621399401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3621399401
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3359009556
Short name T552
Test name
Test status
Simulation time 86216818 ps
CPU time 0.98 seconds
Started Jul 19 04:44:57 PM PDT 24
Finished Jul 19 04:45:03 PM PDT 24
Peak memory 196168 kb
Host smart-14b1daeb-0b53-45ee-b813-5e6e1fc0fdf2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359009556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3359009556
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3067587491
Short name T472
Test name
Test status
Simulation time 293281731 ps
CPU time 4.79 seconds
Started Jul 19 04:44:53 PM PDT 24
Finished Jul 19 04:45:02 PM PDT 24
Peak memory 198140 kb
Host smart-83a2eabd-df79-4b3b-8399-54fa80a57865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067587491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3067587491
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1622587558
Short name T67
Test name
Test status
Simulation time 105717401 ps
CPU time 0.96 seconds
Started Jul 19 04:44:58 PM PDT 24
Finished Jul 19 04:45:04 PM PDT 24
Peak memory 195760 kb
Host smart-97c3a1f0-cf63-4e72-b50b-5514623cf283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622587558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1622587558
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2064385694
Short name T168
Test name
Test status
Simulation time 61091684 ps
CPU time 1.22 seconds
Started Jul 19 04:44:57 PM PDT 24
Finished Jul 19 04:45:03 PM PDT 24
Peak memory 196100 kb
Host smart-aeeb618d-23c3-43c6-afa2-357a88b269d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064385694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2064385694
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.749777631
Short name T4
Test name
Test status
Simulation time 12359117285 ps
CPU time 145.2 seconds
Started Jul 19 04:44:53 PM PDT 24
Finished Jul 19 04:47:23 PM PDT 24
Peak memory 198328 kb
Host smart-104f6ced-9fa9-4360-8110-e8d3609f96de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749777631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.749777631
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.4287733073
Short name T35
Test name
Test status
Simulation time 777133355066 ps
CPU time 3061.86 seconds
Started Jul 19 04:44:51 PM PDT 24
Finished Jul 19 05:35:57 PM PDT 24
Peak memory 198400 kb
Host smart-ac3da699-ecde-4512-a6f5-672f9aaaf98e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4287733073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.4287733073
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.361948386
Short name T327
Test name
Test status
Simulation time 36567577 ps
CPU time 0.62 seconds
Started Jul 19 04:45:02 PM PDT 24
Finished Jul 19 04:45:08 PM PDT 24
Peak memory 194360 kb
Host smart-880d5da5-ed8f-40bb-9fdb-734a79f3f45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361948386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.361948386
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1787552288
Short name T444
Test name
Test status
Simulation time 45566789 ps
CPU time 0.6 seconds
Started Jul 19 04:44:54 PM PDT 24
Finished Jul 19 04:44:59 PM PDT 24
Peak memory 194220 kb
Host smart-4fc6f468-ace2-4524-bacf-e745edc452d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787552288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1787552288
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.574048834
Short name T358
Test name
Test status
Simulation time 1954699302 ps
CPU time 18.38 seconds
Started Jul 19 04:45:00 PM PDT 24
Finished Jul 19 04:45:24 PM PDT 24
Peak memory 195744 kb
Host smart-403e0d1f-8105-43a6-b568-c6a071c25937
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574048834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.574048834
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1477971597
Short name T524
Test name
Test status
Simulation time 114422497 ps
CPU time 0.71 seconds
Started Jul 19 04:44:52 PM PDT 24
Finished Jul 19 04:44:57 PM PDT 24
Peak memory 195864 kb
Host smart-b420cf8b-fff1-4c40-9c7f-05f567d36221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477971597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1477971597
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3350524450
Short name T145
Test name
Test status
Simulation time 202653665 ps
CPU time 1.27 seconds
Started Jul 19 04:44:59 PM PDT 24
Finished Jul 19 04:45:05 PM PDT 24
Peak memory 196060 kb
Host smart-88e36672-8b4a-42c3-8dde-c6a9c98042dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350524450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3350524450
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.578869475
Short name T545
Test name
Test status
Simulation time 328071953 ps
CPU time 3.19 seconds
Started Jul 19 04:45:01 PM PDT 24
Finished Jul 19 04:45:09 PM PDT 24
Peak memory 198256 kb
Host smart-a1c6f789-c355-484e-9814-2f9b7afc502d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578869475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.578869475
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2403875256
Short name T146
Test name
Test status
Simulation time 429279109 ps
CPU time 2.43 seconds
Started Jul 19 04:45:01 PM PDT 24
Finished Jul 19 04:45:08 PM PDT 24
Peak memory 197356 kb
Host smart-9a007e4c-6429-4544-b86e-1b3b593bfd5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403875256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2403875256
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3136743790
Short name T700
Test name
Test status
Simulation time 29964529 ps
CPU time 0.79 seconds
Started Jul 19 04:45:05 PM PDT 24
Finished Jul 19 04:45:10 PM PDT 24
Peak memory 195564 kb
Host smart-6e302051-211d-4bb3-b4d8-f8e9da65eb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136743790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3136743790
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2027110046
Short name T18
Test name
Test status
Simulation time 183663280 ps
CPU time 0.75 seconds
Started Jul 19 04:45:00 PM PDT 24
Finished Jul 19 04:45:06 PM PDT 24
Peak memory 196356 kb
Host smart-677091fa-67b4-44c0-babd-2ca7b6d64b8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027110046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2027110046
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1187994605
Short name T706
Test name
Test status
Simulation time 136089870 ps
CPU time 1.94 seconds
Started Jul 19 04:44:56 PM PDT 24
Finished Jul 19 04:45:02 PM PDT 24
Peak memory 198160 kb
Host smart-58d380d4-193f-46fb-82d7-b86db8a1a542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187994605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1187994605
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2162000075
Short name T133
Test name
Test status
Simulation time 333967274 ps
CPU time 1.54 seconds
Started Jul 19 04:44:53 PM PDT 24
Finished Jul 19 04:44:59 PM PDT 24
Peak memory 197060 kb
Host smart-228c9c85-ea2e-4075-8cd3-68b5d3cc6438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162000075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2162000075
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3609649335
Short name T187
Test name
Test status
Simulation time 85577108 ps
CPU time 1.05 seconds
Started Jul 19 04:45:02 PM PDT 24
Finished Jul 19 04:45:08 PM PDT 24
Peak memory 196024 kb
Host smart-645bfbdf-6587-4f15-89ed-a668c4548c91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609649335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3609649335
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.4052909946
Short name T5
Test name
Test status
Simulation time 14809404637 ps
CPU time 48.81 seconds
Started Jul 19 04:44:50 PM PDT 24
Finished Jul 19 04:45:44 PM PDT 24
Peak memory 198268 kb
Host smart-4fd10b94-1449-417b-ae1e-7f95c4f5fb59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052909946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.4052909946
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1003906624
Short name T326
Test name
Test status
Simulation time 12828292 ps
CPU time 0.56 seconds
Started Jul 19 04:45:09 PM PDT 24
Finished Jul 19 04:45:14 PM PDT 24
Peak memory 194192 kb
Host smart-05cddb2e-a3f8-4a43-9538-17bc635ba386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003906624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1003906624
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.4067277802
Short name T254
Test name
Test status
Simulation time 21498160 ps
CPU time 0.66 seconds
Started Jul 19 04:44:56 PM PDT 24
Finished Jul 19 04:45:01 PM PDT 24
Peak memory 194356 kb
Host smart-edfb09e5-b89a-47d4-86c9-eb74cc43a0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067277802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.4067277802
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1957958664
Short name T516
Test name
Test status
Simulation time 1680673885 ps
CPU time 14.46 seconds
Started Jul 19 04:44:49 PM PDT 24
Finished Jul 19 04:45:08 PM PDT 24
Peak memory 195700 kb
Host smart-d5563291-03c1-4fa9-8667-bca22f0422bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957958664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1957958664
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2799550752
Short name T505
Test name
Test status
Simulation time 41183068 ps
CPU time 0.81 seconds
Started Jul 19 04:45:07 PM PDT 24
Finished Jul 19 04:45:12 PM PDT 24
Peak memory 196904 kb
Host smart-162cc13b-4b3c-4a9a-87ff-b92c68747e27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799550752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2799550752
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1571516224
Short name T194
Test name
Test status
Simulation time 26767528 ps
CPU time 0.88 seconds
Started Jul 19 04:45:07 PM PDT 24
Finished Jul 19 04:45:12 PM PDT 24
Peak memory 196756 kb
Host smart-5de613a9-5d8c-43a3-becc-1e7909005cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571516224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1571516224
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1534445093
Short name T437
Test name
Test status
Simulation time 267647996 ps
CPU time 2.11 seconds
Started Jul 19 04:45:01 PM PDT 24
Finished Jul 19 04:45:08 PM PDT 24
Peak memory 198200 kb
Host smart-1e576251-dde7-4465-bc81-bdd41dfbb74a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534445093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1534445093
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.948718915
Short name T363
Test name
Test status
Simulation time 668467741 ps
CPU time 3.29 seconds
Started Jul 19 04:45:07 PM PDT 24
Finished Jul 19 04:45:15 PM PDT 24
Peak memory 198260 kb
Host smart-cb6b99d5-1da1-40bd-a067-c924fb82a66d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948718915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
948718915
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1996678031
Short name T612
Test name
Test status
Simulation time 24334568 ps
CPU time 0.76 seconds
Started Jul 19 04:45:10 PM PDT 24
Finished Jul 19 04:45:15 PM PDT 24
Peak memory 195700 kb
Host smart-a91e2466-ae64-4c21-9f02-b5695df7acb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996678031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1996678031
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2366357151
Short name T291
Test name
Test status
Simulation time 300336006 ps
CPU time 0.77 seconds
Started Jul 19 04:44:54 PM PDT 24
Finished Jul 19 04:44:59 PM PDT 24
Peak memory 196420 kb
Host smart-17b24c57-d96d-4a83-b266-d861101e507b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366357151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2366357151
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3697444457
Short name T491
Test name
Test status
Simulation time 120682762 ps
CPU time 5.38 seconds
Started Jul 19 04:45:08 PM PDT 24
Finished Jul 19 04:45:17 PM PDT 24
Peak memory 198180 kb
Host smart-4089b149-53bb-42ef-9e71-11e983d4c252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697444457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3697444457
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3254882273
Short name T269
Test name
Test status
Simulation time 171665248 ps
CPU time 1.13 seconds
Started Jul 19 04:45:02 PM PDT 24
Finished Jul 19 04:45:08 PM PDT 24
Peak memory 196500 kb
Host smart-80b3d45b-a4be-4d20-98b8-0201e4d6afad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254882273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3254882273
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1817230765
Short name T474
Test name
Test status
Simulation time 184400389 ps
CPU time 1.05 seconds
Started Jul 19 04:44:51 PM PDT 24
Finished Jul 19 04:44:56 PM PDT 24
Peak memory 195720 kb
Host smart-9c2d37c1-f176-4141-ab1f-edfece58ec78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817230765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1817230765
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.884269451
Short name T487
Test name
Test status
Simulation time 28655848608 ps
CPU time 174.43 seconds
Started Jul 19 04:44:56 PM PDT 24
Finished Jul 19 04:47:55 PM PDT 24
Peak memory 198308 kb
Host smart-9f05e9da-fb84-45fa-95fd-8d404d26cd23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884269451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.884269451
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.90101351
Short name T154
Test name
Test status
Simulation time 37735511 ps
CPU time 0.64 seconds
Started Jul 19 04:43:31 PM PDT 24
Finished Jul 19 04:43:40 PM PDT 24
Peak memory 194372 kb
Host smart-c8b19bc1-4460-48c8-adba-2d349cb1aac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90101351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.90101351
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.34685152
Short name T310
Test name
Test status
Simulation time 105469346 ps
CPU time 0.75 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 195496 kb
Host smart-1c2d05f6-6cc0-45ed-91a4-cf2b69cc0053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34685152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.34685152
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.749383871
Short name T147
Test name
Test status
Simulation time 505819476 ps
CPU time 26.67 seconds
Started Jul 19 04:43:50 PM PDT 24
Finished Jul 19 04:44:20 PM PDT 24
Peak memory 198176 kb
Host smart-e241781d-bf02-4b8c-ad67-340eb7f17bc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749383871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.749383871
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.35581333
Short name T519
Test name
Test status
Simulation time 132158675 ps
CPU time 0.76 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:39 PM PDT 24
Peak memory 195956 kb
Host smart-042ce40e-95f9-4dc5-9129-c001fe5b50cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35581333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.35581333
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.556929903
Short name T302
Test name
Test status
Simulation time 77159964 ps
CPU time 1.3 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:36 PM PDT 24
Peak memory 198232 kb
Host smart-202e4173-4368-466a-9b25-3884b63c3af3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556929903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.556929903
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.933901308
Short name T354
Test name
Test status
Simulation time 82178165 ps
CPU time 2.95 seconds
Started Jul 19 04:43:59 PM PDT 24
Finished Jul 19 04:44:08 PM PDT 24
Peak memory 198256 kb
Host smart-db0a95cd-d787-4b51-af02-4db9b619b47f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933901308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.933901308
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2987388756
Short name T469
Test name
Test status
Simulation time 275524178 ps
CPU time 1.28 seconds
Started Jul 19 04:43:55 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 197732 kb
Host smart-0bc184c1-56b1-4a3c-b78e-b63031dca5dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987388756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2987388756
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1111233119
Short name T334
Test name
Test status
Simulation time 82754248 ps
CPU time 0.94 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:37 PM PDT 24
Peak memory 197012 kb
Host smart-13113c09-3e7a-4b06-a513-7d55d9b95497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111233119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1111233119
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3342445840
Short name T439
Test name
Test status
Simulation time 56411567 ps
CPU time 1.25 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:33 PM PDT 24
Peak memory 198280 kb
Host smart-1ebcd57e-9d6c-4c70-bf7a-a18c52946227
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342445840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3342445840
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3958496776
Short name T193
Test name
Test status
Simulation time 164672155 ps
CPU time 3.7 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:41 PM PDT 24
Peak memory 198220 kb
Host smart-c829ba97-5bb0-4ac2-8c09-8bf3c9954781
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958496776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3958496776
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2974865159
Short name T582
Test name
Test status
Simulation time 104937805 ps
CPU time 0.86 seconds
Started Jul 19 04:43:19 PM PDT 24
Finished Jul 19 04:43:22 PM PDT 24
Peak memory 196564 kb
Host smart-ce12099e-2990-41b0-a94a-c4e4d58c1910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974865159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2974865159
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.349765061
Short name T389
Test name
Test status
Simulation time 89885178 ps
CPU time 1.04 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:39 PM PDT 24
Peak memory 195772 kb
Host smart-bd33f239-841c-4d15-a353-cf214e50d4c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349765061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.349765061
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1921745141
Short name T568
Test name
Test status
Simulation time 16639439299 ps
CPU time 173.5 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:46:29 PM PDT 24
Peak memory 198276 kb
Host smart-9a889a6e-5737-4edd-b24c-e795f60360a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921745141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1921745141
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3406765323
Short name T563
Test name
Test status
Simulation time 19280177 ps
CPU time 0.55 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 194144 kb
Host smart-aca6cfba-8f78-4c31-8859-3ceb180186b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406765323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3406765323
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1506284195
Short name T276
Test name
Test status
Simulation time 34859434 ps
CPU time 0.85 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:36 PM PDT 24
Peak memory 196256 kb
Host smart-5ad6653e-5913-4236-bbc5-94d01ce32e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506284195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1506284195
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2266091897
Short name T500
Test name
Test status
Simulation time 469327156 ps
CPU time 23.91 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:55 PM PDT 24
Peak memory 198288 kb
Host smart-b30b6b7c-953d-4e98-88b1-f082614fc490
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266091897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2266091897
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2486999113
Short name T442
Test name
Test status
Simulation time 319171858 ps
CPU time 0.98 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:36 PM PDT 24
Peak memory 197964 kb
Host smart-2c6a90ac-865b-40a4-9a07-5391157be47d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486999113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2486999113
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.589017511
Short name T704
Test name
Test status
Simulation time 53927462 ps
CPU time 1.35 seconds
Started Jul 19 04:43:27 PM PDT 24
Finished Jul 19 04:43:34 PM PDT 24
Peak memory 198336 kb
Host smart-2eb8f968-f3b8-4396-888e-46a5358836c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589017511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.589017511
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1855203889
Short name T567
Test name
Test status
Simulation time 87407125 ps
CPU time 1.01 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 196304 kb
Host smart-7bbbc42f-3316-426c-bf93-68aae31cb474
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855203889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1855203889
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1303560676
Short name T479
Test name
Test status
Simulation time 320866735 ps
CPU time 1.88 seconds
Started Jul 19 04:43:33 PM PDT 24
Finished Jul 19 04:43:42 PM PDT 24
Peak memory 195964 kb
Host smart-790d0ae6-4493-4efa-97e4-a15864c1d695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303560676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1303560676
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1566434334
Short name T467
Test name
Test status
Simulation time 17441443 ps
CPU time 0.65 seconds
Started Jul 19 04:43:25 PM PDT 24
Finished Jul 19 04:43:30 PM PDT 24
Peak memory 194416 kb
Host smart-24336a51-fc5a-4eb7-a88f-53591e10b6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566434334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1566434334
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2320159939
Short name T429
Test name
Test status
Simulation time 48031184 ps
CPU time 0.75 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 196204 kb
Host smart-5407f87d-463f-4415-8b46-cd372fdb45dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320159939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2320159939
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.133522942
Short name T378
Test name
Test status
Simulation time 674215080 ps
CPU time 2.25 seconds
Started Jul 19 04:43:35 PM PDT 24
Finished Jul 19 04:43:44 PM PDT 24
Peak memory 198196 kb
Host smart-1daec2c6-e858-45c2-ac54-5926aec0c368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133522942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.133522942
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3568006319
Short name T386
Test name
Test status
Simulation time 341398270 ps
CPU time 0.92 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:35 PM PDT 24
Peak memory 195888 kb
Host smart-153bf933-b914-4071-92b5-efff561cd332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568006319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3568006319
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.559513431
Short name T181
Test name
Test status
Simulation time 202707505 ps
CPU time 1.05 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 195904 kb
Host smart-b96ef774-be3a-4522-8205-944c1feb5a73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559513431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.559513431
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3540004997
Short name T395
Test name
Test status
Simulation time 10775151953 ps
CPU time 149.9 seconds
Started Jul 19 04:43:37 PM PDT 24
Finished Jul 19 04:46:13 PM PDT 24
Peak memory 198320 kb
Host smart-134c938e-c690-4d92-82a8-cdd581af30b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540004997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3540004997
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.977234454
Short name T58
Test name
Test status
Simulation time 156325129 ps
CPU time 0.59 seconds
Started Jul 19 04:43:31 PM PDT 24
Finished Jul 19 04:43:39 PM PDT 24
Peak memory 194852 kb
Host smart-91ea71c7-026e-44e3-9607-861df7bd0655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977234454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.977234454
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3666537599
Short name T387
Test name
Test status
Simulation time 48949711 ps
CPU time 0.86 seconds
Started Jul 19 04:43:34 PM PDT 24
Finished Jul 19 04:43:42 PM PDT 24
Peak memory 196496 kb
Host smart-79e34262-9376-4ab9-82ff-4e7781d4c175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666537599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3666537599
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2694706331
Short name T144
Test name
Test status
Simulation time 5789650347 ps
CPU time 25.4 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:58 PM PDT 24
Peak memory 197132 kb
Host smart-20b85ea7-974a-4dad-88f1-dc75ef882e79
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694706331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2694706331
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3793221850
Short name T262
Test name
Test status
Simulation time 75126981 ps
CPU time 1.08 seconds
Started Jul 19 04:43:24 PM PDT 24
Finished Jul 19 04:43:28 PM PDT 24
Peak memory 198416 kb
Host smart-709d0c1e-9392-4e9d-9d8a-510750befa19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793221850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3793221850
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.985304776
Short name T316
Test name
Test status
Simulation time 63305787 ps
CPU time 1.12 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:37 PM PDT 24
Peak memory 196284 kb
Host smart-8d508716-2643-4753-b9dd-6e2124821509
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985304776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.985304776
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3487068635
Short name T201
Test name
Test status
Simulation time 271003667 ps
CPU time 2.66 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 198300 kb
Host smart-6ab9c1f6-8805-49ee-b931-3b5db7afd7ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487068635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3487068635
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2474768374
Short name T188
Test name
Test status
Simulation time 160316447 ps
CPU time 1.68 seconds
Started Jul 19 04:43:25 PM PDT 24
Finished Jul 19 04:43:30 PM PDT 24
Peak memory 196012 kb
Host smart-dbedf9e4-73c6-49ee-9225-924adb6a25b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474768374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2474768374
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.220464217
Short name T455
Test name
Test status
Simulation time 110291932 ps
CPU time 1.18 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:36 PM PDT 24
Peak memory 196752 kb
Host smart-fd2e1033-afc6-40b2-9fcf-807b355d4a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220464217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.220464217
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.732341313
Short name T328
Test name
Test status
Simulation time 56285488 ps
CPU time 0.62 seconds
Started Jul 19 04:43:35 PM PDT 24
Finished Jul 19 04:43:43 PM PDT 24
Peak memory 195148 kb
Host smart-1ac53c21-1307-4f78-abac-4e41300651ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732341313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.732341313
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2498638551
Short name T602
Test name
Test status
Simulation time 100198686 ps
CPU time 4.14 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:42 PM PDT 24
Peak memory 198156 kb
Host smart-5457110d-55b8-4a6e-b3bc-4d15a13cabe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498638551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2498638551
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3356716696
Short name T213
Test name
Test status
Simulation time 458882712 ps
CPU time 1.25 seconds
Started Jul 19 04:43:41 PM PDT 24
Finished Jul 19 04:43:48 PM PDT 24
Peak memory 196800 kb
Host smart-e7040779-93f3-4958-a433-1afd227e7dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356716696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3356716696
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3506878457
Short name T205
Test name
Test status
Simulation time 45856163 ps
CPU time 1.2 seconds
Started Jul 19 04:43:32 PM PDT 24
Finished Jul 19 04:43:41 PM PDT 24
Peak memory 196912 kb
Host smart-87c17874-3708-4e64-b580-69cbca2285fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506878457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3506878457
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.85269130
Short name T247
Test name
Test status
Simulation time 21153942333 ps
CPU time 69.99 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:44:40 PM PDT 24
Peak memory 198296 kb
Host smart-94c5772a-5601-4f90-a4ae-d22505b175ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85269130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpi
o_stress_all.85269130
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2075994589
Short name T61
Test name
Test status
Simulation time 268599216892 ps
CPU time 2702.65 seconds
Started Jul 19 04:43:34 PM PDT 24
Finished Jul 19 05:28:44 PM PDT 24
Peak memory 198424 kb
Host smart-3f356ae0-4bc8-4852-b685-3f1d549b1c0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2075994589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2075994589
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3148412268
Short name T207
Test name
Test status
Simulation time 15300949 ps
CPU time 0.58 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:36 PM PDT 24
Peak memory 194384 kb
Host smart-488048d0-0cdb-4b16-8773-dd606a20fa4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148412268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3148412268
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2171317070
Short name T251
Test name
Test status
Simulation time 17787284 ps
CPU time 0.66 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:32 PM PDT 24
Peak memory 194188 kb
Host smart-f48998cb-d124-4b1c-bf4c-753eb1e91ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171317070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2171317070
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.585152533
Short name T416
Test name
Test status
Simulation time 1737303361 ps
CPU time 27.98 seconds
Started Jul 19 04:43:24 PM PDT 24
Finished Jul 19 04:43:54 PM PDT 24
Peak memory 196784 kb
Host smart-34dff439-b19e-40cb-8dd9-0fad6fc5c4e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585152533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.585152533
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2772764027
Short name T17
Test name
Test status
Simulation time 87009137 ps
CPU time 1 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:36 PM PDT 24
Peak memory 196948 kb
Host smart-d35c11de-83a2-4734-9c79-d98bf7637f73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772764027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2772764027
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1828169009
Short name T346
Test name
Test status
Simulation time 174539787 ps
CPU time 1.27 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:37 PM PDT 24
Peak memory 197448 kb
Host smart-7bf4e7e9-6b7b-47b1-84ee-bd18a23dd62e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828169009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1828169009
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1861338542
Short name T566
Test name
Test status
Simulation time 79120182 ps
CPU time 1.82 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:32 PM PDT 24
Peak memory 198264 kb
Host smart-339a3cdc-a2a8-4381-bcb9-87d483642e32
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861338542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1861338542
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3649321323
Short name T287
Test name
Test status
Simulation time 140734642 ps
CPU time 1.64 seconds
Started Jul 19 04:43:25 PM PDT 24
Finished Jul 19 04:43:30 PM PDT 24
Peak memory 196952 kb
Host smart-7d94d46b-951a-4263-9e0e-4464aa41c9e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649321323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3649321323
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.450307338
Short name T321
Test name
Test status
Simulation time 68273357 ps
CPU time 0.93 seconds
Started Jul 19 04:43:25 PM PDT 24
Finished Jul 19 04:43:30 PM PDT 24
Peak memory 196128 kb
Host smart-528af563-035c-4f15-95c2-f04d337b0401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450307338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.450307338
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3743977249
Short name T688
Test name
Test status
Simulation time 37648860 ps
CPU time 0.87 seconds
Started Jul 19 04:43:43 PM PDT 24
Finished Jul 19 04:43:50 PM PDT 24
Peak memory 196208 kb
Host smart-a2f2d92c-9f4e-4da2-b426-bf79503d655b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743977249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3743977249
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1505078934
Short name T99
Test name
Test status
Simulation time 836977649 ps
CPU time 4.61 seconds
Started Jul 19 04:43:28 PM PDT 24
Finished Jul 19 04:43:40 PM PDT 24
Peak memory 198164 kb
Host smart-faf360d2-87e9-4789-81c7-f6e0d045139c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505078934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1505078934
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1070112859
Short name T601
Test name
Test status
Simulation time 143945781 ps
CPU time 1.04 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:41 PM PDT 24
Peak memory 196696 kb
Host smart-95a12ac9-e9a3-4f13-ad6f-93eb9326dab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070112859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1070112859
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1003215412
Short name T470
Test name
Test status
Simulation time 867740701 ps
CPU time 1.31 seconds
Started Jul 19 04:43:25 PM PDT 24
Finished Jul 19 04:43:30 PM PDT 24
Peak memory 196868 kb
Host smart-f0a06c59-dd40-4264-9d1f-30866c3a55d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003215412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1003215412
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3892331737
Short name T684
Test name
Test status
Simulation time 8644248659 ps
CPU time 49.72 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:44:27 PM PDT 24
Peak memory 198372 kb
Host smart-1d3983d8-e144-47a0-9ba7-75ddd446edaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892331737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3892331737
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3780093607
Short name T64
Test name
Test status
Simulation time 80541213876 ps
CPU time 1708.02 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 05:12:04 PM PDT 24
Peak memory 198488 kb
Host smart-28b3c1f6-48f1-470d-8b71-7d96c05a98e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3780093607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3780093607
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4120260697
Short name T670
Test name
Test status
Simulation time 38253896 ps
CPU time 0.54 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 194188 kb
Host smart-bc8b436a-eec0-4578-a37e-20e62ac3ddb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120260697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4120260697
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3087396367
Short name T364
Test name
Test status
Simulation time 50114904 ps
CPU time 0.75 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 196192 kb
Host smart-a078fdae-e745-4129-8c56-077012d58daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087396367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3087396367
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1283346219
Short name T699
Test name
Test status
Simulation time 755271768 ps
CPU time 21.87 seconds
Started Jul 19 04:43:40 PM PDT 24
Finished Jul 19 04:44:07 PM PDT 24
Peak memory 197024 kb
Host smart-cf81863e-c731-41f7-8ae3-60f837999a69
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283346219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1283346219
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.428765673
Short name T476
Test name
Test status
Simulation time 86648633 ps
CPU time 0.99 seconds
Started Jul 19 04:43:31 PM PDT 24
Finished Jul 19 04:43:40 PM PDT 24
Peak memory 196556 kb
Host smart-a295bea0-32df-4bb3-81dd-e34c06bc53b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428765673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.428765673
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3456717262
Short name T509
Test name
Test status
Simulation time 81956258 ps
CPU time 1.23 seconds
Started Jul 19 04:43:25 PM PDT 24
Finished Jul 19 04:43:29 PM PDT 24
Peak memory 198292 kb
Host smart-e0a2df69-5c57-45b3-a36a-ad3f497fd23d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456717262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3456717262
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3156963035
Short name T662
Test name
Test status
Simulation time 599695780 ps
CPU time 2.76 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:41 PM PDT 24
Peak memory 196540 kb
Host smart-dbb75943-14d2-4c58-b0b7-f3a246411a73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156963035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3156963035
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.859902077
Short name T508
Test name
Test status
Simulation time 663894980 ps
CPU time 3.07 seconds
Started Jul 19 04:43:31 PM PDT 24
Finished Jul 19 04:43:42 PM PDT 24
Peak memory 196788 kb
Host smart-7a502a0d-d62b-4906-97f1-cff2ec9808e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859902077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.859902077
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1874035495
Short name T367
Test name
Test status
Simulation time 57602328 ps
CPU time 0.66 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:38 PM PDT 24
Peak memory 194380 kb
Host smart-8672ebcc-c1d5-40f3-b29e-15294eee70f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874035495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1874035495
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3756819945
Short name T179
Test name
Test status
Simulation time 162540938 ps
CPU time 0.86 seconds
Started Jul 19 04:43:29 PM PDT 24
Finished Jul 19 04:43:37 PM PDT 24
Peak memory 196824 kb
Host smart-e9370828-2ac8-492a-82e7-80754ebfa971
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756819945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3756819945
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1330490519
Short name T397
Test name
Test status
Simulation time 1444435575 ps
CPU time 5.54 seconds
Started Jul 19 04:43:30 PM PDT 24
Finished Jul 19 04:43:43 PM PDT 24
Peak memory 198184 kb
Host smart-1b17ee11-0bff-47a6-97eb-bf5e3f5afa03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330490519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1330490519
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4088876166
Short name T619
Test name
Test status
Simulation time 52623514 ps
CPU time 1.02 seconds
Started Jul 19 04:43:27 PM PDT 24
Finished Jul 19 04:43:34 PM PDT 24
Peak memory 195764 kb
Host smart-e992a7c5-1411-4853-9c3a-2155fc11006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088876166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4088876166
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3687501798
Short name T22
Test name
Test status
Simulation time 924572911 ps
CPU time 1.13 seconds
Started Jul 19 04:43:26 PM PDT 24
Finished Jul 19 04:43:31 PM PDT 24
Peak memory 195832 kb
Host smart-d6f51bd1-c0dc-41ec-966b-4e5974e4baac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687501798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3687501798
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.508456727
Short name T32
Test name
Test status
Simulation time 94725547729 ps
CPU time 161.01 seconds
Started Jul 19 04:43:33 PM PDT 24
Finished Jul 19 04:46:22 PM PDT 24
Peak memory 198324 kb
Host smart-2e193a0a-58e1-400d-a71e-eb1f95488564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508456727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.508456727
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1699755992
Short name T853
Test name
Test status
Simulation time 91685544 ps
CPU time 0.72 seconds
Started Jul 19 04:30:50 PM PDT 24
Finished Jul 19 04:30:58 PM PDT 24
Peak memory 196576 kb
Host smart-8f152117-4633-42b5-bc65-14a56ffe1e0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1699755992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1699755992
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2583090313
Short name T865
Test name
Test status
Simulation time 112554180 ps
CPU time 0.99 seconds
Started Jul 19 04:30:54 PM PDT 24
Finished Jul 19 04:31:09 PM PDT 24
Peak memory 192036 kb
Host smart-f600c8ae-7bfc-4102-9117-f1398fc36755
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583090313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2583090313
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.347485369
Short name T850
Test name
Test status
Simulation time 53993239 ps
CPU time 1.38 seconds
Started Jul 19 04:30:54 PM PDT 24
Finished Jul 19 04:31:10 PM PDT 24
Peak memory 192356 kb
Host smart-acfdf980-c04f-468f-9caa-9e31d6da12f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=347485369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.347485369
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1733442201
Short name T907
Test name
Test status
Simulation time 196685657 ps
CPU time 0.87 seconds
Started Jul 19 04:30:52 PM PDT 24
Finished Jul 19 04:31:06 PM PDT 24
Peak memory 197740 kb
Host smart-2493bdc7-3f32-4cd5-a508-dee61d4fc45d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733442201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1733442201
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2419139387
Short name T919
Test name
Test status
Simulation time 142666658 ps
CPU time 1.27 seconds
Started Jul 19 04:30:50 PM PDT 24
Finished Jul 19 04:31:02 PM PDT 24
Peak memory 192112 kb
Host smart-91b06577-1252-43c5-98fc-36ba12851256
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2419139387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2419139387
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043859747
Short name T909
Test name
Test status
Simulation time 78980446 ps
CPU time 1.37 seconds
Started Jul 19 04:30:56 PM PDT 24
Finished Jul 19 04:31:13 PM PDT 24
Peak memory 192064 kb
Host smart-9c9c9faa-340c-4a16-ade7-1813d0f5479f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043859747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3043859747
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1887857206
Short name T931
Test name
Test status
Simulation time 153846378 ps
CPU time 0.97 seconds
Started Jul 19 04:30:56 PM PDT 24
Finished Jul 19 04:31:13 PM PDT 24
Peak memory 196776 kb
Host smart-8533fa2c-dbe7-4b0d-b7cb-3a0d6a136e93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1887857206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1887857206
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1502995719
Short name T885
Test name
Test status
Simulation time 140138454 ps
CPU time 1.36 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:22 PM PDT 24
Peak memory 192076 kb
Host smart-64cb1b17-b7ba-410b-9437-fe429675903b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502995719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1502995719
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4258551162
Short name T917
Test name
Test status
Simulation time 36528169 ps
CPU time 1.06 seconds
Started Jul 19 04:30:50 PM PDT 24
Finished Jul 19 04:30:58 PM PDT 24
Peak memory 192072 kb
Host smart-417a9813-3aff-4641-9750-054138cdd293
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4258551162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.4258551162
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1422484696
Short name T884
Test name
Test status
Simulation time 211890742 ps
CPU time 1.1 seconds
Started Jul 19 04:30:53 PM PDT 24
Finished Jul 19 04:31:08 PM PDT 24
Peak memory 191624 kb
Host smart-5300b07c-4e8f-40bc-a584-880c3aeff882
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422484696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1422484696
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.897642685
Short name T880
Test name
Test status
Simulation time 157945210 ps
CPU time 1.23 seconds
Started Jul 19 04:31:00 PM PDT 24
Finished Jul 19 04:31:18 PM PDT 24
Peak memory 192020 kb
Host smart-9449b095-c7f8-462e-85b2-aef87a370950
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=897642685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.897642685
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2470798913
Short name T845
Test name
Test status
Simulation time 90208274 ps
CPU time 0.76 seconds
Started Jul 19 04:30:54 PM PDT 24
Finished Jul 19 04:31:10 PM PDT 24
Peak memory 191904 kb
Host smart-1f533d3f-5113-4794-a371-df7882b8c946
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470798913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2470798913
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.178759590
Short name T902
Test name
Test status
Simulation time 269858463 ps
CPU time 1.22 seconds
Started Jul 19 04:30:54 PM PDT 24
Finished Jul 19 04:31:11 PM PDT 24
Peak memory 198388 kb
Host smart-9680df80-f274-498f-a2c9-ff2f6bb88e6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=178759590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.178759590
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.969688486
Short name T936
Test name
Test status
Simulation time 169021133 ps
CPU time 1.24 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:13 PM PDT 24
Peak memory 192044 kb
Host smart-2a68fd1b-eabf-474e-9817-b6372441c5cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969688486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.969688486
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.562948334
Short name T871
Test name
Test status
Simulation time 247279836 ps
CPU time 1.24 seconds
Started Jul 19 04:30:52 PM PDT 24
Finished Jul 19 04:31:07 PM PDT 24
Peak memory 192076 kb
Host smart-451278b6-14d6-4899-9086-ecbd143dad2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=562948334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.562948334
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2033716088
Short name T924
Test name
Test status
Simulation time 89331955 ps
CPU time 0.78 seconds
Started Jul 19 04:30:54 PM PDT 24
Finished Jul 19 04:31:11 PM PDT 24
Peak memory 191900 kb
Host smart-0f348927-a64c-4a12-8a83-a6fff2ecffeb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033716088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2033716088
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.936318085
Short name T899
Test name
Test status
Simulation time 43361926 ps
CPU time 0.86 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:22 PM PDT 24
Peak memory 191912 kb
Host smart-7da73020-4240-437a-ae9c-e4af37dab7d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=936318085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.936318085
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2094986902
Short name T844
Test name
Test status
Simulation time 74086269 ps
CPU time 1.12 seconds
Started Jul 19 04:30:54 PM PDT 24
Finished Jul 19 04:31:11 PM PDT 24
Peak memory 192100 kb
Host smart-9ef53761-30e2-4322-9d50-9c8933c5aaa0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094986902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2094986902
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1774844782
Short name T913
Test name
Test status
Simulation time 83565555 ps
CPU time 1.21 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:12 PM PDT 24
Peak memory 198436 kb
Host smart-33fabb5e-863c-46a4-8cc8-4fe75ba9b81f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1774844782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1774844782
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4077155211
Short name T897
Test name
Test status
Simulation time 757761619 ps
CPU time 1.32 seconds
Started Jul 19 04:30:53 PM PDT 24
Finished Jul 19 04:31:09 PM PDT 24
Peak memory 191608 kb
Host smart-934caa9a-3a1b-40b3-a3b8-7a204ccf4705
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077155211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4077155211
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2758751478
Short name T852
Test name
Test status
Simulation time 130672402 ps
CPU time 1.26 seconds
Started Jul 19 04:30:53 PM PDT 24
Finished Jul 19 04:31:08 PM PDT 24
Peak memory 192060 kb
Host smart-f72b7d62-aaee-4484-b203-a04c2a987b7e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2758751478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2758751478
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750866327
Short name T855
Test name
Test status
Simulation time 71375945 ps
CPU time 1.04 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:11 PM PDT 24
Peak memory 192044 kb
Host smart-0665938a-5a70-4824-bfc0-1c99007c900f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750866327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2750866327
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3831108290
Short name T930
Test name
Test status
Simulation time 332637844 ps
CPU time 1.32 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:12 PM PDT 24
Peak memory 192076 kb
Host smart-492cca72-f3a1-4692-b947-42a73a9d29e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3831108290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3831108290
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4241155842
Short name T868
Test name
Test status
Simulation time 270754918 ps
CPU time 1.25 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:12 PM PDT 24
Peak memory 192076 kb
Host smart-bccbae06-53a9-4c13-9cfd-cab6f7c0233f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241155842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4241155842
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1646231204
Short name T873
Test name
Test status
Simulation time 90151028 ps
CPU time 1.05 seconds
Started Jul 19 04:30:54 PM PDT 24
Finished Jul 19 04:31:09 PM PDT 24
Peak memory 192320 kb
Host smart-ad973db5-5091-43fe-b166-86b3b3db9b2e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1646231204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1646231204
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.804371695
Short name T939
Test name
Test status
Simulation time 77074516 ps
CPU time 1.46 seconds
Started Jul 19 04:30:51 PM PDT 24
Finished Jul 19 04:31:04 PM PDT 24
Peak memory 192080 kb
Host smart-c9a0ef9a-6f0d-4ea4-bbef-cee1f674b280
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804371695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.804371695
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3178868058
Short name T933
Test name
Test status
Simulation time 47419248 ps
CPU time 1.28 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:12 PM PDT 24
Peak memory 192096 kb
Host smart-4e75e113-b103-4949-abf9-5dacb5f59d29
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3178868058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3178868058
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2438967335
Short name T891
Test name
Test status
Simulation time 254436331 ps
CPU time 1.27 seconds
Started Jul 19 04:30:51 PM PDT 24
Finished Jul 19 04:31:03 PM PDT 24
Peak memory 192076 kb
Host smart-88feec86-a117-42e7-9aae-273f160eb16f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438967335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2438967335
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.359984116
Short name T888
Test name
Test status
Simulation time 166818804 ps
CPU time 0.83 seconds
Started Jul 19 04:30:52 PM PDT 24
Finished Jul 19 04:31:06 PM PDT 24
Peak memory 191896 kb
Host smart-7d581b37-e87c-44bc-a870-0ed765e319c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=359984116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.359984116
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3555109915
Short name T854
Test name
Test status
Simulation time 34232023 ps
CPU time 0.9 seconds
Started Jul 19 04:31:43 PM PDT 24
Finished Jul 19 04:31:51 PM PDT 24
Peak memory 191904 kb
Host smart-01dbd640-1f03-40de-9318-93875aee5e0b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555109915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3555109915
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2562055930
Short name T857
Test name
Test status
Simulation time 67393622 ps
CPU time 1.17 seconds
Started Jul 19 04:30:58 PM PDT 24
Finished Jul 19 04:31:16 PM PDT 24
Peak memory 198424 kb
Host smart-3c8edc97-8479-4e8a-900b-e4ee89bbe74f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2562055930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2562055930
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3422866246
Short name T935
Test name
Test status
Simulation time 167610231 ps
CPU time 1.34 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:12 PM PDT 24
Peak memory 192060 kb
Host smart-cd1a201b-0c2c-4d53-a3cc-bf2d2701ddbd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422866246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3422866246
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2724545692
Short name T894
Test name
Test status
Simulation time 46963987 ps
CPU time 1.12 seconds
Started Jul 19 04:30:58 PM PDT 24
Finished Jul 19 04:31:16 PM PDT 24
Peak memory 198420 kb
Host smart-7f329b6e-4da7-46f6-a6b5-fde4b671d63c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2724545692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2724545692
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3350536827
Short name T920
Test name
Test status
Simulation time 44840396 ps
CPU time 1.25 seconds
Started Jul 19 04:30:58 PM PDT 24
Finished Jul 19 04:31:16 PM PDT 24
Peak memory 198396 kb
Host smart-4b92abb9-46e9-4da6-9e8b-6396274a8b68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350536827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3350536827
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3158697490
Short name T890
Test name
Test status
Simulation time 105754320 ps
CPU time 1.11 seconds
Started Jul 19 04:30:54 PM PDT 24
Finished Jul 19 04:31:11 PM PDT 24
Peak memory 192276 kb
Host smart-070bb1c8-044c-46a6-a911-f23a5af52125
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3158697490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3158697490
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3228790742
Short name T893
Test name
Test status
Simulation time 39484645 ps
CPU time 1.06 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:11 PM PDT 24
Peak memory 198384 kb
Host smart-86f600a9-9c98-4419-8867-ed31411cf1f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228790742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3228790742
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3955985210
Short name T904
Test name
Test status
Simulation time 175289138 ps
CPU time 1.07 seconds
Started Jul 19 04:30:59 PM PDT 24
Finished Jul 19 04:31:17 PM PDT 24
Peak memory 192148 kb
Host smart-6ae92615-1ee9-4506-b82a-9fe9d1a3b080
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3955985210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3955985210
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.822425403
Short name T937
Test name
Test status
Simulation time 76034574 ps
CPU time 1.39 seconds
Started Jul 19 04:31:00 PM PDT 24
Finished Jul 19 04:31:18 PM PDT 24
Peak memory 198460 kb
Host smart-b86fc969-57ca-474c-9ae9-7d61f8194350
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822425403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.822425403
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2654678971
Short name T901
Test name
Test status
Simulation time 152445595 ps
CPU time 0.94 seconds
Started Jul 19 04:31:01 PM PDT 24
Finished Jul 19 04:31:19 PM PDT 24
Peak memory 192092 kb
Host smart-34408094-1fcf-4174-adfe-32501fd273ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2654678971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2654678971
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4104332483
Short name T870
Test name
Test status
Simulation time 532319603 ps
CPU time 1.26 seconds
Started Jul 19 04:30:58 PM PDT 24
Finished Jul 19 04:31:16 PM PDT 24
Peak memory 198448 kb
Host smart-37994e9f-3734-4ce9-8062-edf0fc05bd6d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104332483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4104332483
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2198210612
Short name T847
Test name
Test status
Simulation time 184225873 ps
CPU time 1.35 seconds
Started Jul 19 04:30:59 PM PDT 24
Finished Jul 19 04:31:17 PM PDT 24
Peak memory 192072 kb
Host smart-5d0e81d3-3327-48e4-9d62-414f97def14c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2198210612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2198210612
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.341021669
Short name T918
Test name
Test status
Simulation time 93871729 ps
CPU time 0.79 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:22 PM PDT 24
Peak memory 191896 kb
Host smart-21c2db57-0c8f-44f4-9ede-0d7e7ee78c05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341021669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.341021669
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.90506403
Short name T895
Test name
Test status
Simulation time 204617503 ps
CPU time 1.28 seconds
Started Jul 19 04:30:59 PM PDT 24
Finished Jul 19 04:31:17 PM PDT 24
Peak memory 192076 kb
Host smart-eeb479a3-f792-40a4-aeda-aeadb80e7c8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=90506403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.90506403
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3733518405
Short name T921
Test name
Test status
Simulation time 245396597 ps
CPU time 1.27 seconds
Started Jul 19 04:30:59 PM PDT 24
Finished Jul 19 04:31:17 PM PDT 24
Peak memory 192120 kb
Host smart-0df22703-dd15-4476-b8d4-9a6923b14310
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733518405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3733518405
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3665584030
Short name T887
Test name
Test status
Simulation time 381231254 ps
CPU time 0.96 seconds
Started Jul 19 04:31:00 PM PDT 24
Finished Jul 19 04:31:17 PM PDT 24
Peak memory 191972 kb
Host smart-535e6cb1-326f-49b7-857a-af857e1eb58e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3665584030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3665584030
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2829119610
Short name T896
Test name
Test status
Simulation time 650265014 ps
CPU time 0.93 seconds
Started Jul 19 04:30:58 PM PDT 24
Finished Jul 19 04:31:16 PM PDT 24
Peak memory 197564 kb
Host smart-f6edd489-39b0-48af-9855-7cc08971cfeb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829119610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2829119610
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2326550772
Short name T872
Test name
Test status
Simulation time 49624624 ps
CPU time 0.75 seconds
Started Jul 19 04:31:12 PM PDT 24
Finished Jul 19 04:31:29 PM PDT 24
Peak memory 191916 kb
Host smart-336f4636-2d25-4e67-9f47-be539e6e2d46
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2326550772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2326550772
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.100153379
Short name T866
Test name
Test status
Simulation time 163213348 ps
CPU time 1.34 seconds
Started Jul 19 04:30:52 PM PDT 24
Finished Jul 19 04:31:06 PM PDT 24
Peak memory 192060 kb
Host smart-ebe8fea9-e7d0-486d-ad49-edc1a8a4ae14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100153379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.100153379
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.605254905
Short name T927
Test name
Test status
Simulation time 119003125 ps
CPU time 1.2 seconds
Started Jul 19 04:31:05 PM PDT 24
Finished Jul 19 04:31:23 PM PDT 24
Peak memory 192060 kb
Host smart-b871d8f7-7c64-4195-93cd-d9944bf91ad1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=605254905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.605254905
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2788463223
Short name T874
Test name
Test status
Simulation time 49108366 ps
CPU time 1.28 seconds
Started Jul 19 04:31:00 PM PDT 24
Finished Jul 19 04:31:18 PM PDT 24
Peak memory 192064 kb
Host smart-705ddf3b-7012-4f68-a15d-b29441fcf88b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788463223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2788463223
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2795134733
Short name T876
Test name
Test status
Simulation time 392326630 ps
CPU time 1.17 seconds
Started Jul 19 04:31:01 PM PDT 24
Finished Jul 19 04:31:19 PM PDT 24
Peak memory 192072 kb
Host smart-8e72eb6d-4463-49e1-8cc9-573a55c9b0ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2795134733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2795134733
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1630275503
Short name T916
Test name
Test status
Simulation time 61733172 ps
CPU time 1.01 seconds
Started Jul 19 04:31:00 PM PDT 24
Finished Jul 19 04:31:18 PM PDT 24
Peak memory 197868 kb
Host smart-ca211df5-fc90-43d3-a044-4abc6cab3113
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630275503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1630275503
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3054516445
Short name T889
Test name
Test status
Simulation time 85533120 ps
CPU time 1.23 seconds
Started Jul 19 04:30:59 PM PDT 24
Finished Jul 19 04:31:17 PM PDT 24
Peak memory 192064 kb
Host smart-56fb43b5-26f0-433a-9764-8b3d0ac842d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3054516445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3054516445
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2579274187
Short name T849
Test name
Test status
Simulation time 83782433 ps
CPU time 0.72 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:24 PM PDT 24
Peak memory 191796 kb
Host smart-f6e89439-43cf-4bad-ab14-98baf1a92d23
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579274187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2579274187
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.729579308
Short name T886
Test name
Test status
Simulation time 155083890 ps
CPU time 0.89 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:21 PM PDT 24
Peak memory 191900 kb
Host smart-c268e5f0-a38e-4ad8-a63f-b6059b96f38f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=729579308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.729579308
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1874596878
Short name T841
Test name
Test status
Simulation time 232511782 ps
CPU time 1.08 seconds
Started Jul 19 04:31:02 PM PDT 24
Finished Jul 19 04:31:20 PM PDT 24
Peak memory 192076 kb
Host smart-87175db7-2ad8-4a22-9025-321a6016f74c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874596878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1874596878
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3206218262
Short name T862
Test name
Test status
Simulation time 143898479 ps
CPU time 0.98 seconds
Started Jul 19 04:31:03 PM PDT 24
Finished Jul 19 04:31:21 PM PDT 24
Peak memory 197844 kb
Host smart-13d4a046-a967-4a2d-b74d-71f4286033a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3206218262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3206218262
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1446314662
Short name T882
Test name
Test status
Simulation time 95147989 ps
CPU time 0.82 seconds
Started Jul 19 04:31:01 PM PDT 24
Finished Jul 19 04:31:18 PM PDT 24
Peak memory 196484 kb
Host smart-6767bd0e-691c-4529-b66f-313e3a1dc5e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446314662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1446314662
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4161606451
Short name T932
Test name
Test status
Simulation time 121060873 ps
CPU time 1.35 seconds
Started Jul 19 04:31:01 PM PDT 24
Finished Jul 19 04:31:20 PM PDT 24
Peak memory 192252 kb
Host smart-06844e82-c9fd-4baa-ba08-9c0c97cd3f95
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4161606451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4161606451
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.876617265
Short name T915
Test name
Test status
Simulation time 36721723 ps
CPU time 0.99 seconds
Started Jul 19 04:31:02 PM PDT 24
Finished Jul 19 04:31:20 PM PDT 24
Peak memory 192068 kb
Host smart-0caa1364-6894-4b45-aa1c-927ca54ce9cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876617265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.876617265
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3987019320
Short name T869
Test name
Test status
Simulation time 77783266 ps
CPU time 1.35 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:24 PM PDT 24
Peak memory 191996 kb
Host smart-391737a6-4e53-4124-bfd4-9410e3d434e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3987019320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3987019320
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2534661506
Short name T900
Test name
Test status
Simulation time 240852125 ps
CPU time 1.06 seconds
Started Jul 19 04:31:07 PM PDT 24
Finished Jul 19 04:31:25 PM PDT 24
Peak memory 192096 kb
Host smart-ab9f9d08-b2d5-4b48-bd93-8657121afce3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534661506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2534661506
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.920669033
Short name T928
Test name
Test status
Simulation time 228023950 ps
CPU time 1.04 seconds
Started Jul 19 04:31:02 PM PDT 24
Finished Jul 19 04:31:20 PM PDT 24
Peak memory 192072 kb
Host smart-0561e0f5-50aa-417e-86f0-dc35bfa2b957
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=920669033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.920669033
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4067481465
Short name T925
Test name
Test status
Simulation time 35171508 ps
CPU time 0.94 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 191904 kb
Host smart-e02ffe14-7c73-4a7b-af83-a972f4013613
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067481465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4067481465
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3371580011
Short name T911
Test name
Test status
Simulation time 136382425 ps
CPU time 1.23 seconds
Started Jul 19 04:31:19 PM PDT 24
Finished Jul 19 04:31:37 PM PDT 24
Peak memory 192104 kb
Host smart-944a6806-f966-45a1-80ab-7608620c2563
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3371580011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3371580011
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.984841415
Short name T922
Test name
Test status
Simulation time 1921604878 ps
CPU time 1.5 seconds
Started Jul 19 04:31:00 PM PDT 24
Finished Jul 19 04:31:18 PM PDT 24
Peak memory 192052 kb
Host smart-a9cfaf0d-f10b-4160-81f8-16e0b1996cbd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984841415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.984841415
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2157875917
Short name T858
Test name
Test status
Simulation time 122818102 ps
CPU time 1.19 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:24 PM PDT 24
Peak memory 198428 kb
Host smart-f6cfcad9-a2cf-45ea-8dc7-413785423b3c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2157875917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2157875917
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1306186795
Short name T864
Test name
Test status
Simulation time 80818832 ps
CPU time 1.24 seconds
Started Jul 19 04:31:07 PM PDT 24
Finished Jul 19 04:31:25 PM PDT 24
Peak memory 198336 kb
Host smart-ace8c05e-97f2-4b0d-8dce-0811e5f4db91
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306186795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1306186795
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.42654434
Short name T906
Test name
Test status
Simulation time 93609722 ps
CPU time 0.94 seconds
Started Jul 19 04:30:51 PM PDT 24
Finished Jul 19 04:31:04 PM PDT 24
Peak memory 191904 kb
Host smart-2c17c1d3-b7aa-406f-b0e9-82133c9bf11c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=42654434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.42654434
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1242099208
Short name T923
Test name
Test status
Simulation time 82852528 ps
CPU time 1.21 seconds
Started Jul 19 04:30:53 PM PDT 24
Finished Jul 19 04:31:09 PM PDT 24
Peak memory 192068 kb
Host smart-23112efb-ae16-411b-9d74-97168065d915
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242099208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1242099208
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3699205085
Short name T929
Test name
Test status
Simulation time 62604850 ps
CPU time 1.07 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:24 PM PDT 24
Peak memory 191764 kb
Host smart-6054585f-5f46-4ace-9049-56679cfe6641
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3699205085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3699205085
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1110335077
Short name T867
Test name
Test status
Simulation time 76587304 ps
CPU time 1.3 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:22 PM PDT 24
Peak memory 192072 kb
Host smart-5b4844b5-c6df-4427-a721-c9516e8bf55b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110335077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1110335077
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2004537450
Short name T940
Test name
Test status
Simulation time 69183061 ps
CPU time 1.23 seconds
Started Jul 19 04:31:08 PM PDT 24
Finished Jul 19 04:31:26 PM PDT 24
Peak memory 192072 kb
Host smart-862b1377-f361-475a-9048-90dadadacb6d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2004537450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2004537450
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3377251961
Short name T846
Test name
Test status
Simulation time 233705566 ps
CPU time 1.01 seconds
Started Jul 19 04:31:13 PM PDT 24
Finished Jul 19 04:31:30 PM PDT 24
Peak memory 192052 kb
Host smart-feab52a4-6844-4918-9f62-98853646afed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377251961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3377251961
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2662801929
Short name T842
Test name
Test status
Simulation time 78115403 ps
CPU time 1.1 seconds
Started Jul 19 04:31:14 PM PDT 24
Finished Jul 19 04:31:31 PM PDT 24
Peak memory 198464 kb
Host smart-d453861a-6e10-4aff-b6cc-e29377995f2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2662801929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2662801929
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2064257200
Short name T938
Test name
Test status
Simulation time 204531682 ps
CPU time 1.22 seconds
Started Jul 19 04:31:17 PM PDT 24
Finished Jul 19 04:31:34 PM PDT 24
Peak memory 192120 kb
Host smart-7da9a8f8-aeee-40bb-928f-5f6aee313d9a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064257200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2064257200
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3874609306
Short name T914
Test name
Test status
Simulation time 113251645 ps
CPU time 0.78 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:36 PM PDT 24
Peak memory 191884 kb
Host smart-09f2f00b-0133-4bc8-bbd7-bacb0e013bf8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3874609306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3874609306
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.878240538
Short name T877
Test name
Test status
Simulation time 71968304 ps
CPU time 1.15 seconds
Started Jul 19 04:31:16 PM PDT 24
Finished Jul 19 04:31:33 PM PDT 24
Peak memory 192092 kb
Host smart-522c8276-af15-4a68-aaa8-f88295f017fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878240538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.878240538
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.962621711
Short name T905
Test name
Test status
Simulation time 71109953 ps
CPU time 0.87 seconds
Started Jul 19 04:31:17 PM PDT 24
Finished Jul 19 04:31:33 PM PDT 24
Peak memory 196672 kb
Host smart-fa7fcc89-3990-4aca-88d7-19e157e3bcd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=962621711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.962621711
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2129266487
Short name T863
Test name
Test status
Simulation time 47428728 ps
CPU time 0.9 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 191856 kb
Host smart-3d6e6003-268d-4e2b-9206-fcde6553ae03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129266487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2129266487
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3805843369
Short name T848
Test name
Test status
Simulation time 55515357 ps
CPU time 0.68 seconds
Started Jul 19 04:31:07 PM PDT 24
Finished Jul 19 04:31:25 PM PDT 24
Peak memory 191872 kb
Host smart-93877962-9af9-414c-a32f-bf61dff491a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3805843369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3805843369
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.521655820
Short name T843
Test name
Test status
Simulation time 225395980 ps
CPU time 1.22 seconds
Started Jul 19 04:31:21 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 192032 kb
Host smart-77b94486-df56-4c9a-9f36-82a260d6f822
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521655820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.521655820
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.112698615
Short name T859
Test name
Test status
Simulation time 39475086 ps
CPU time 1.07 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:24 PM PDT 24
Peak memory 191876 kb
Host smart-e805f414-ef52-4222-b1e8-1ed263a67ab4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=112698615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.112698615
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1952401143
Short name T912
Test name
Test status
Simulation time 96624458 ps
CPU time 1.34 seconds
Started Jul 19 04:31:09 PM PDT 24
Finished Jul 19 04:31:27 PM PDT 24
Peak memory 192088 kb
Host smart-b7943b7d-4711-44d8-a9d1-5f548a0eb946
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952401143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1952401143
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.624920735
Short name T892
Test name
Test status
Simulation time 48845697 ps
CPU time 1.26 seconds
Started Jul 19 04:31:23 PM PDT 24
Finished Jul 19 04:31:41 PM PDT 24
Peak memory 192048 kb
Host smart-c8fabed3-3337-47de-9be5-5247e65a01f6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=624920735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.624920735
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3608357000
Short name T856
Test name
Test status
Simulation time 55873563 ps
CPU time 1.02 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:41 PM PDT 24
Peak memory 192040 kb
Host smart-3f0695c1-2a57-43aa-8337-d2c02c46859e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608357000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3608357000
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.739011720
Short name T926
Test name
Test status
Simulation time 25978488 ps
CPU time 0.75 seconds
Started Jul 19 04:31:10 PM PDT 24
Finished Jul 19 04:31:28 PM PDT 24
Peak memory 191896 kb
Host smart-bb64798c-733c-4dc8-b761-b70ab2405f1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=739011720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.739011720
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1111069122
Short name T875
Test name
Test status
Simulation time 162942279 ps
CPU time 1.2 seconds
Started Jul 19 04:31:29 PM PDT 24
Finished Jul 19 04:31:46 PM PDT 24
Peak memory 192004 kb
Host smart-c5d41aa8-41b6-4351-a94f-8aa6a330b012
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111069122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1111069122
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.201704968
Short name T879
Test name
Test status
Simulation time 132608730 ps
CPU time 0.91 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 191840 kb
Host smart-f2bc322f-d59b-4a14-8da9-40143ff1e6ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=201704968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.201704968
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2396851690
Short name T934
Test name
Test status
Simulation time 76809979 ps
CPU time 1.12 seconds
Started Jul 19 04:31:29 PM PDT 24
Finished Jul 19 04:31:46 PM PDT 24
Peak memory 192040 kb
Host smart-784ee591-7205-43e7-9925-f3e28ae4ac2a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396851690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2396851690
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4205732886
Short name T910
Test name
Test status
Simulation time 75513578 ps
CPU time 1.3 seconds
Started Jul 19 04:30:50 PM PDT 24
Finished Jul 19 04:31:02 PM PDT 24
Peak memory 192096 kb
Host smart-166f3852-10a6-43fc-bee9-2adf781f291c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4205732886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.4205732886
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3257088765
Short name T881
Test name
Test status
Simulation time 50617640 ps
CPU time 1.08 seconds
Started Jul 19 04:30:56 PM PDT 24
Finished Jul 19 04:31:14 PM PDT 24
Peak memory 197904 kb
Host smart-71367886-8c7a-44d9-ad81-d882c86b3fed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257088765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3257088765
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2114479663
Short name T851
Test name
Test status
Simulation time 228017290 ps
CPU time 1.19 seconds
Started Jul 19 04:30:52 PM PDT 24
Finished Jul 19 04:31:06 PM PDT 24
Peak memory 198472 kb
Host smart-78b1f36e-f063-4117-9705-c26132d02c7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2114479663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2114479663
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2340876983
Short name T908
Test name
Test status
Simulation time 84170184 ps
CPU time 1.28 seconds
Started Jul 19 04:30:49 PM PDT 24
Finished Jul 19 04:30:55 PM PDT 24
Peak memory 198484 kb
Host smart-ade91ca4-bd43-49a7-a3ed-fe1141459e7d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340876983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2340876983
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2479540339
Short name T878
Test name
Test status
Simulation time 191159792 ps
CPU time 1.03 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:13 PM PDT 24
Peak memory 191792 kb
Host smart-878a6aff-bdc4-4439-a504-2a18f8509e95
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2479540339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2479540339
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2905191928
Short name T903
Test name
Test status
Simulation time 133420692 ps
CPU time 0.92 seconds
Started Jul 19 04:30:50 PM PDT 24
Finished Jul 19 04:30:58 PM PDT 24
Peak memory 191912 kb
Host smart-3d74d6cc-d5f9-416e-ba4b-55e557d30a81
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905191928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2905191928
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.106045121
Short name T860
Test name
Test status
Simulation time 43662878 ps
CPU time 1.17 seconds
Started Jul 19 04:30:54 PM PDT 24
Finished Jul 19 04:31:11 PM PDT 24
Peak memory 192048 kb
Host smart-a14f3aa5-6117-44d9-a66d-ede9c9e81340
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=106045121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.106045121
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3147611954
Short name T883
Test name
Test status
Simulation time 102921074 ps
CPU time 0.77 seconds
Started Jul 19 04:30:49 PM PDT 24
Finished Jul 19 04:30:54 PM PDT 24
Peak memory 191896 kb
Host smart-0c838ef2-59e1-49a7-b9f3-21402aad5d1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147611954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3147611954
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.974212623
Short name T861
Test name
Test status
Simulation time 191400477 ps
CPU time 1.22 seconds
Started Jul 19 04:30:49 PM PDT 24
Finished Jul 19 04:30:55 PM PDT 24
Peak memory 198464 kb
Host smart-505d2baf-589c-47ae-82e3-b66a3f2aad91
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=974212623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.974212623
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3539810087
Short name T898
Test name
Test status
Simulation time 83691180 ps
CPU time 1.31 seconds
Started Jul 19 04:30:55 PM PDT 24
Finished Jul 19 04:31:13 PM PDT 24
Peak memory 191780 kb
Host smart-57c66351-41fe-4d64-aec9-80f9650610d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539810087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3539810087
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%