Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4312647	1			T31	43188		T32	117		T19	36
all_pins[1]	4312647	1			T31	43188		T32	117		T19	36
all_pins[2]	4312647	1			T31	43188		T32	117		T19	36
all_pins[3]	4312647	1			T31	43188		T32	117		T19	36
all_pins[4]	4312647	1			T31	43188		T32	117		T19	36
all_pins[5]	4312647	1			T31	43188		T32	117		T19	36
all_pins[6]	4312647	1			T31	43188		T32	117		T19	36
all_pins[7]	4312647	1			T31	43188		T32	117		T19	36
all_pins[8]	4312647	1			T31	43188		T32	117		T19	36
all_pins[9]	4312647	1			T31	43188		T32	117		T19	36
all_pins[10]	4312647	1			T31	43188		T32	117		T19	36
all_pins[11]	4312647	1			T31	43188		T32	117		T19	36
all_pins[12]	4312647	1			T31	43188		T32	117		T19	36
all_pins[13]	4312647	1			T31	43188		T32	117		T19	36
all_pins[14]	4312647	1			T31	43188		T32	117		T19	36
all_pins[15]	4312647	1			T31	43188		T32	117		T19	36
all_pins[16]	4312647	1			T31	43188		T32	117		T19	36
all_pins[17]	4312647	1			T31	43188		T32	117		T19	36
all_pins[18]	4312647	1			T31	43188		T32	117		T19	36
all_pins[19]	4312647	1			T31	43188		T32	117		T19	36
all_pins[20]	4312647	1			T31	43188		T32	117		T19	36
all_pins[21]	4312647	1			T31	43188		T32	117		T19	36
all_pins[22]	4312647	1			T31	43188		T32	117		T19	36
all_pins[23]	4312647	1			T31	43188		T32	117		T19	36
all_pins[24]	4312647	1			T31	43188		T32	117		T19	36
all_pins[25]	4312647	1			T31	43188		T32	117		T19	36
all_pins[26]	4312647	1			T31	43188		T32	117		T19	36
all_pins[27]	4312647	1			T31	43188		T32	117		T19	36
all_pins[28]	4312647	1			T31	43188		T32	117		T19	36
all_pins[29]	4312647	1			T31	43188		T32	117		T19	36
all_pins[30]	4312647	1			T31	43188		T32	117		T19	36
all_pins[31]	4312647	1			T31	43188		T32	117		T19	36

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	85737165	1			T31	856201		T32	2304		T19	930
values[0x1]	52267539	1			T31	525815		T32	1440		T19	222
transitions[0x0=>0x1]	31321270	1			T31	313830		T32	883		T19	145
transitions[0x1=>0x0]	31321105	1			T31	313830		T32	883		T19	145

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2682656	1			T31	27040		T32	74		T19	27
all_pins[0]	values[0x1]	1629991	1			T31	16148		T32	43		T19	9
all_pins[0]	transitions[0x0=>0x1]	1010518	1			T31	10089		T32	21		T19	6
all_pins[0]	transitions[0x1=>0x0]	1011648	1			T31	10155		T32	14		T19	6
all_pins[1]	values[0x0]	2676678	1			T31	26759		T32	71		T19	28
all_pins[1]	values[0x1]	1635969	1			T31	16429		T32	46		T19	8
all_pins[1]	transitions[0x0=>0x1]	980281	1			T31	10092		T32	30		T19	4
all_pins[1]	transitions[0x1=>0x0]	974303	1			T31	9811		T32	27		T19	5
all_pins[2]	values[0x0]	2685339	1			T31	26578		T32	45		T19	32
all_pins[2]	values[0x1]	1627308	1			T31	16610		T32	72		T19	4
all_pins[2]	transitions[0x0=>0x1]	972310	1			T31	9649		T32	45		T19	3
all_pins[2]	transitions[0x1=>0x0]	980971	1			T31	9468		T32	19		T19	7
all_pins[3]	values[0x0]	2676291	1			T31	26481		T32	77		T19	31
all_pins[3]	values[0x1]	1636356	1			T31	16707		T32	40		T19	5
all_pins[3]	transitions[0x0=>0x1]	984059	1			T31	9919		T32	20		T19	5
all_pins[3]	transitions[0x1=>0x0]	975011	1			T31	9822		T32	52		T19	4
all_pins[4]	values[0x0]	2678938	1			T31	26754		T32	60		T19	30
all_pins[4]	values[0x1]	1633709	1			T31	16434		T32	57		T19	6
all_pins[4]	transitions[0x0=>0x1]	976686	1			T31	9724		T32	34		T19	4
all_pins[4]	transitions[0x1=>0x0]	979333	1			T31	9997		T32	17		T19	3
all_pins[5]	values[0x0]	2673064	1			T31	26904		T32	80		T19	32
all_pins[5]	values[0x1]	1639583	1			T31	16284		T32	37		T19	4
all_pins[5]	transitions[0x0=>0x1]	981215	1			T31	9711		T32	15		T22	238
all_pins[5]	transitions[0x1=>0x0]	975341	1			T31	9861		T32	35		T19	2
all_pins[6]	values[0x0]	2680141	1			T31	26397		T32	48		T19	34
all_pins[6]	values[0x1]	1632506	1			T31	16791		T32	69		T19	2
all_pins[6]	transitions[0x0=>0x1]	974325	1			T31	10189		T32	49		T19	2
all_pins[6]	transitions[0x1=>0x0]	981402	1			T31	9682		T32	17		T19	4
all_pins[7]	values[0x0]	2683157	1			T31	26557		T32	63		T19	32
all_pins[7]	values[0x1]	1629490	1			T31	16631		T32	54		T19	4
all_pins[7]	transitions[0x0=>0x1]	978838	1			T31	9593		T32	14		T19	4
all_pins[7]	transitions[0x1=>0x0]	981854	1			T31	9753		T32	29		T19	2
all_pins[8]	values[0x0]	2681690	1			T31	26479		T32	60		T19	35
all_pins[8]	values[0x1]	1630957	1			T31	16709		T32	57		T19	1
all_pins[8]	transitions[0x0=>0x1]	977925	1			T31	9903		T32	32		T22	335
all_pins[8]	transitions[0x1=>0x0]	976458	1			T31	9825		T32	29		T19	3
all_pins[9]	values[0x0]	2676320	1			T31	26742		T32	77		T19	28
all_pins[9]	values[0x1]	1636327	1			T31	16446		T32	40		T19	8
all_pins[9]	transitions[0x0=>0x1]	983148	1			T31	9669		T32	21		T19	8
all_pins[9]	transitions[0x1=>0x0]	977778	1			T31	9932		T32	38		T19	1
all_pins[10]	values[0x0]	2678601	1			T31	26920		T32	60		T19	22
all_pins[10]	values[0x1]	1634046	1			T31	16268		T32	57		T19	14
all_pins[10]	transitions[0x0=>0x1]	977520	1			T31	9652		T32	34		T19	9
all_pins[10]	transitions[0x1=>0x0]	979801	1			T31	9830		T32	17		T19	3
all_pins[11]	values[0x0]	2674344	1			T31	26811		T32	94		T19	24
all_pins[11]	values[0x1]	1638303	1			T31	16377		T32	23		T19	12
all_pins[11]	transitions[0x0=>0x1]	980321	1			T31	9960		T32	13		T19	5
all_pins[11]	transitions[0x1=>0x0]	976064	1			T31	9851		T32	47		T19	7
all_pins[12]	values[0x0]	2678817	1			T31	27065		T32	69		T19	23
all_pins[12]	values[0x1]	1633830	1			T31	16123		T32	48		T19	13
all_pins[12]	transitions[0x0=>0x1]	974281	1			T31	9460		T32	38		T19	5
all_pins[12]	transitions[0x1=>0x0]	978754	1			T31	9714		T32	13		T19	4
all_pins[13]	values[0x0]	2677564	1			T31	26643		T32	72		T19	28
all_pins[13]	values[0x1]	1635083	1			T31	16545		T32	45		T19	8
all_pins[13]	transitions[0x0=>0x1]	976262	1			T31	9936		T32	27		T19	2
all_pins[13]	transitions[0x1=>0x0]	975009	1			T31	9514		T32	30		T19	7
all_pins[14]	values[0x0]	2679365	1			T31	26322		T32	71		T19	33
all_pins[14]	values[0x1]	1633282	1			T31	16866		T32	46		T19	3
all_pins[14]	transitions[0x0=>0x1]	977570	1			T31	10086		T32	27		T19	3
all_pins[14]	transitions[0x1=>0x0]	979371	1			T31	9765		T32	26		T19	8
all_pins[15]	values[0x0]	2677876	1			T31	26966		T32	68		T19	23
all_pins[15]	values[0x1]	1634771	1			T31	16222		T32	49		T19	13
all_pins[15]	transitions[0x0=>0x1]	978604	1			T31	9525		T32	27		T19	12
all_pins[15]	transitions[0x1=>0x0]	977115	1			T31	10169		T32	24		T19	2
all_pins[16]	values[0x0]	2677861	1			T31	26912		T32	77		T19	32
all_pins[16]	values[0x1]	1634786	1			T31	16276		T32	40		T19	4
all_pins[16]	transitions[0x0=>0x1]	980337	1			T31	9857		T32	27		T19	2
all_pins[16]	transitions[0x1=>0x0]	980322	1			T31	9803		T32	36		T19	11
all_pins[17]	values[0x0]	2676625	1			T31	26878		T32	79		T19	36
all_pins[17]	values[0x1]	1636022	1			T31	16310		T32	38		T22	365
all_pins[17]	transitions[0x0=>0x1]	978295	1			T31	9653		T32	22		T22	214
all_pins[17]	transitions[0x1=>0x0]	977059	1			T31	9619		T32	24		T19	4
all_pins[18]	values[0x0]	2682452	1			T31	26906		T32	99		T19	29
all_pins[18]	values[0x1]	1630195	1			T31	16282		T32	18		T19	7
all_pins[18]	transitions[0x0=>0x1]	973668	1			T31	9778		T32	13		T19	7
all_pins[18]	transitions[0x1=>0x0]	979495	1			T31	9806		T32	33		T22	205
all_pins[19]	values[0x0]	2680205	1			T31	26711		T32	70		T19	31
all_pins[19]	values[0x1]	1632442	1			T31	16477		T32	47		T19	5
all_pins[19]	transitions[0x0=>0x1]	976937	1			T31	9943		T32	39		T19	5
all_pins[19]	transitions[0x1=>0x0]	974690	1			T31	9748		T32	10		T19	7
all_pins[20]	values[0x0]	2676646	1			T31	26639		T32	67		T19	31
all_pins[20]	values[0x1]	1636001	1			T31	16549		T32	50		T19	5
all_pins[20]	transitions[0x0=>0x1]	980047	1			T31	10187		T32	31		T19	2
all_pins[20]	transitions[0x1=>0x0]	976488	1			T31	10115		T32	28		T19	2
all_pins[21]	values[0x0]	2677412	1			T31	26399		T32	82		T19	27
all_pins[21]	values[0x1]	1635235	1			T31	16789		T32	35		T19	9
all_pins[21]	transitions[0x0=>0x1]	977727	1			T31	9912		T32	24		T19	6
all_pins[21]	transitions[0x1=>0x0]	978493	1			T31	9672		T32	39		T19	2
all_pins[22]	values[0x0]	2677419	1			T31	26392		T32	62		T19	29
all_pins[22]	values[0x1]	1635228	1			T31	16796		T32	55		T19	7
all_pins[22]	transitions[0x0=>0x1]	977188	1			T31	9818		T32	39		T19	1
all_pins[22]	transitions[0x1=>0x0]	977195	1			T31	9811		T32	19		T19	3
all_pins[23]	values[0x0]	2677911	1			T31	27188		T32	66		T19	31
all_pins[23]	values[0x1]	1634736	1			T31	16000		T32	51		T19	5
all_pins[23]	transitions[0x0=>0x1]	979397	1			T31	9403		T32	29		T19	4
all_pins[23]	transitions[0x1=>0x0]	979889	1			T31	10199		T32	33		T19	6
all_pins[24]	values[0x0]	2687177	1			T31	27159		T32	86		T19	35
all_pins[24]	values[0x1]	1625470	1			T31	16029		T32	31		T19	1
all_pins[24]	transitions[0x0=>0x1]	972804	1			T31	9657		T32	15		T19	1
all_pins[24]	transitions[0x1=>0x0]	982070	1			T31	9628		T32	35		T19	5
all_pins[25]	values[0x0]	2682075	1			T31	26475		T32	67		T19	21
all_pins[25]	values[0x1]	1630572	1			T31	16713		T32	50		T19	15
all_pins[25]	transitions[0x0=>0x1]	978405	1			T31	10033		T32	37		T19	14
all_pins[25]	transitions[0x1=>0x0]	973303	1			T31	9349		T32	18		T22	185
all_pins[26]	values[0x0]	2678327	1			T31	26643		T32	74		T19	29
all_pins[26]	values[0x1]	1634320	1			T31	16545		T32	43		T19	7
all_pins[26]	transitions[0x0=>0x1]	977504	1			T31	9634		T32	24		T19	2
all_pins[26]	transitions[0x1=>0x0]	973756	1			T31	9802		T32	31		T19	10
all_pins[27]	values[0x0]	2680909	1			T31	27080		T32	93		T19	22
all_pins[27]	values[0x1]	1631738	1			T31	16108		T32	24		T19	14
all_pins[27]	transitions[0x0=>0x1]	976749	1			T31	9556		T32	22		T19	10
all_pins[27]	transitions[0x1=>0x0]	979331	1			T31	9993		T32	41		T19	3
all_pins[28]	values[0x0]	2677816	1			T31	26773		T32	82		T19	32
all_pins[28]	values[0x1]	1634831	1			T31	16415		T32	35		T19	4
all_pins[28]	transitions[0x0=>0x1]	976471	1			T31	9940		T32	24		T22	264
all_pins[28]	transitions[0x1=>0x0]	973378	1			T31	9633		T32	13		T19	10
all_pins[29]	values[0x0]	2680173	1			T31	27021		T32	63		T19	27
all_pins[29]	values[0x1]	1632474	1			T31	16167		T32	54		T19	9
all_pins[29]	transitions[0x0=>0x1]	975985	1			T31	9742		T32	35		T19	6
all_pins[29]	transitions[0x1=>0x0]	978342	1			T31	9990		T32	16		T19	1
all_pins[30]	values[0x0]	2681955	1			T31	26633		T32	67		T19	29
all_pins[30]	values[0x1]	1630692	1			T31	16555		T32	50		T19	7
all_pins[30]	transitions[0x0=>0x1]	977081	1			T31	9921		T32	27		T19	7
all_pins[30]	transitions[0x1=>0x0]	978863	1			T31	9533		T32	31		T19	9
all_pins[31]	values[0x0]	2681361	1			T31	26974		T32	81		T19	27
all_pins[31]	values[0x1]	1631286	1			T31	16214		T32	36		T19	9
all_pins[31]	transitions[0x0=>0x1]	978812	1			T31	9639		T32	28		T19	6
all_pins[31]	transitions[0x1=>0x0]	978218	1			T31	9980		T32	42		T19	4