Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14208394	1			T31	136903		T32	351		T19	58
all_values[1]	14208394	1			T31	136903		T32	351		T19	58
all_values[2]	14208394	1			T31	136903		T32	351		T19	58
all_values[3]	14208394	1			T31	136903		T32	351		T19	58
all_values[4]	14208394	1			T31	136903		T32	351		T19	58
all_values[5]	14208394	1			T31	136903		T32	351		T19	58
all_values[6]	14208394	1			T31	136903		T32	351		T19	58
all_values[7]	14208394	1			T31	136903		T32	351		T19	58
all_values[8]	14208394	1			T31	136903		T32	351		T19	58
all_values[9]	14208394	1			T31	136903		T32	351		T19	58
all_values[10]	14208394	1			T31	136903		T32	351		T19	58
all_values[11]	14208394	1			T31	136903		T32	351		T19	58
all_values[12]	14208394	1			T31	136903		T32	351		T19	58
all_values[13]	14208394	1			T31	136903		T32	351		T19	58
all_values[14]	14208394	1			T31	136903		T32	351		T19	58
all_values[15]	14208394	1			T31	136903		T32	351		T19	58
all_values[16]	14208394	1			T31	136903		T32	351		T19	58
all_values[17]	14208394	1			T31	136903		T32	351		T19	58
all_values[18]	14208394	1			T31	136903		T32	351		T19	58
all_values[19]	14208394	1			T31	136903		T32	351		T19	58
all_values[20]	14208394	1			T31	136903		T32	351		T19	58
all_values[21]	14208394	1			T31	136903		T32	351		T19	58
all_values[22]	14208394	1			T31	136903		T32	351		T19	58
all_values[23]	14208394	1			T31	136903		T32	351		T19	58
all_values[24]	14208394	1			T31	136903		T32	351		T19	58
all_values[25]	14208394	1			T31	136903		T32	351		T19	58
all_values[26]	14208394	1			T31	136903		T32	351		T19	58
all_values[27]	14208394	1			T31	136903		T32	351		T19	58
all_values[28]	14208394	1			T31	136903		T32	351		T19	58
all_values[29]	14208394	1			T31	136903		T32	351		T19	58
all_values[30]	14208394	1			T31	136903		T32	351		T19	58
all_values[31]	14208394	1			T31	136903		T32	351		T19	58

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

261941849

1

T31

238630

T32

5737

T19

1313

auto[1]

192726759

1

T31

199459

T32

5495

T19

543

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106455739

1

T31

773342

T32

1340

T19

1201

auto[1]

348212869

1

T31

360755

T32

9892

T19

655

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

449668153

1

T31

432838

T32

10767

T19

1759

auto[1]

5000455

1

T31

52507

T32

465

T19

97

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2738090	1			T31	18202		T32	18		T19	25
all_values[0]	auto[0]	auto[0]	auto[1]	5387018	1			T31	57707		T32	191		T19	12
all_values[0]	auto[0]	auto[1]	auto[0]	583576	1			T31	5746		T32	19		T19	5
all_values[0]	auto[0]	auto[1]	auto[1]	5343251	1			T31	53614		T32	111		T19	11
all_values[0]	auto[1]	auto[0]	auto[1]	78964	1			T31	832		T32	7		T19	3
all_values[0]	auto[1]	auto[1]	auto[1]	77495	1			T31	802		T32	5		T19	2
all_values[1]	auto[0]	auto[0]	auto[0]	2732259	1			T31	18673		T32	29		T19	23
all_values[1]	auto[0]	auto[0]	auto[1]	5368077	1			T31	53225		T32	131		T19	19
all_values[1]	auto[0]	auto[1]	auto[0]	591361	1			T31	6571		T32	31		T22	128
all_values[1]	auto[0]	auto[1]	auto[1]	5359708	1			T31	56802		T32	144		T19	11
all_values[1]	auto[1]	auto[0]	auto[1]	78402	1			T31	792		T32	9		T19	4
all_values[1]	auto[1]	auto[1]	auto[1]	78587	1			T31	840		T32	7		T19	1
all_values[2]	auto[0]	auto[0]	auto[0]	2737456	1			T31	17714		T32	4		T19	29
all_values[2]	auto[0]	auto[0]	auto[1]	5391718	1			T31	55592		T32	98		T19	4
all_values[2]	auto[0]	auto[1]	auto[0]	583014	1			T31	6352		T32	19		T19	18
all_values[2]	auto[0]	auto[1]	auto[1]	5340027	1			T31	55584		T32	213		T19	4
all_values[2]	auto[1]	auto[0]	auto[1]	78670	1			T31	837		T32	3		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	77509	1			T31	824		T32	14		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	2751250	1			T31	18207		T32	48		T19	25
all_values[3]	auto[0]	auto[0]	auto[1]	5339846	1			T31	53660		T32	134		T19	22
all_values[3]	auto[0]	auto[1]	auto[0]	595270	1			T31	5863		T32	28		T22	199
all_values[3]	auto[0]	auto[1]	auto[1]	5366021	1			T31	57508		T32	128		T19	7
all_values[3]	auto[1]	auto[0]	auto[1]	77659	1			T31	839		T32	7		T19	3
all_values[3]	auto[1]	auto[1]	auto[1]	78348	1			T31	826		T32	6		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	2735953	1			T31	18402		T32	6		T19	32
all_values[4]	auto[0]	auto[0]	auto[1]	5347485	1			T31	54382		T32	106		T19	4
all_values[4]	auto[0]	auto[1]	auto[0]	592528	1			T31	6163		T32	24		T19	13
all_values[4]	auto[0]	auto[1]	auto[1]	5376069	1			T31	56309		T32	202		T19	7
all_values[4]	auto[1]	auto[0]	auto[1]	78313	1			T31	818		T32	6		T19	1
all_values[4]	auto[1]	auto[1]	auto[1]	78046	1			T31	829		T32	7		T19	1
all_values[5]	auto[0]	auto[0]	auto[0]	2738386	1			T31	18258		T32	35		T19	38
all_values[5]	auto[0]	auto[0]	auto[1]	5337453	1			T31	55597		T32	172		T19	12
all_values[5]	auto[0]	auto[1]	auto[0]	588025	1			T31	6034		T32	8		T22	67
all_values[5]	auto[0]	auto[1]	auto[1]	5388631	1			T31	55301		T32	116		T19	4
all_values[5]	auto[1]	auto[0]	auto[1]	78342	1			T31	861		T32	12		T19	3
all_values[5]	auto[1]	auto[1]	auto[1]	77557	1			T31	852		T32	8		T19	1
all_values[6]	auto[0]	auto[0]	auto[0]	2737589	1			T31	17788		T32	33		T19	29
all_values[6]	auto[0]	auto[0]	auto[1]	5372505	1			T31	53432		T32	38		T19	11
all_values[6]	auto[0]	auto[1]	auto[0]	596903	1			T31	5951		T32	23		T19	14
all_values[6]	auto[0]	auto[1]	auto[1]	5344935	1			T31	58083		T32	242		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	78317	1			T31	822		T32	3		T19	2
all_values[6]	auto[1]	auto[1]	auto[1]	78145	1			T31	827		T32	12		T19	1
all_values[7]	auto[0]	auto[0]	auto[0]	2747686	1			T31	18075		T32	20		T19	35
all_values[7]	auto[0]	auto[0]	auto[1]	5376510	1			T31	55970		T32	74		T19	5
all_values[7]	auto[0]	auto[1]	auto[0]	601990	1			T31	5865		T32	43		T19	11
all_values[7]	auto[0]	auto[1]	auto[1]	5325933	1			T31	55317		T32	199		T19	5
all_values[7]	auto[1]	auto[0]	auto[1]	78593	1			T31	845		T32	3		T19	1
all_values[7]	auto[1]	auto[1]	auto[1]	77682	1			T31	831		T32	12		T19	1
all_values[8]	auto[0]	auto[0]	auto[0]	2743190	1			T31	18297		T32	24		T19	31
all_values[8]	auto[0]	auto[0]	auto[1]	5368875	1			T31	55534		T32	97		T19	16
all_values[8]	auto[0]	auto[1]	auto[0]	587090	1			T31	6012		T32	22		T19	7
all_values[8]	auto[0]	auto[1]	auto[1]	5352940	1			T31	55445		T32	194		T22	1625
all_values[8]	auto[1]	auto[0]	auto[1]	78749	1			T31	814		T32	3		T19	3
all_values[8]	auto[1]	auto[1]	auto[1]	77550	1			T31	801		T32	11		T19	1
all_values[9]	auto[0]	auto[0]	auto[0]	2738873	1			T31	17802		T32	23		T19	28
all_values[9]	auto[0]	auto[0]	auto[1]	5365626	1			T31	54179		T32	146		T19	18
all_values[9]	auto[0]	auto[1]	auto[0]	583637	1			T31	6407		T32	18		T19	2
all_values[9]	auto[0]	auto[1]	auto[1]	5363785	1			T31	56842		T32	149		T19	6
all_values[9]	auto[1]	auto[0]	auto[1]	78363	1			T31	851		T32	10		T19	2
all_values[9]	auto[1]	auto[1]	auto[1]	78110	1			T31	822		T32	5		T19	2
all_values[10]	auto[0]	auto[0]	auto[0]	2743897	1			T31	17775		T32	3		T19	26
all_values[10]	auto[0]	auto[0]	auto[1]	5349203	1			T31	54786		T32	157		T19	2
all_values[10]	auto[0]	auto[1]	auto[0]	588851	1			T31	6081		T32	10		T19	10
all_values[10]	auto[0]	auto[1]	auto[1]	5370179	1			T31	56618		T32	169		T19	14
all_values[10]	auto[1]	auto[0]	auto[1]	78475	1			T31	814		T32	4		T27	2312
all_values[10]	auto[1]	auto[1]	auto[1]	77789	1			T31	829		T32	8		T19	6
all_values[11]	auto[0]	auto[0]	auto[0]	2737871	1			T31	17959		T32	83		T19	25
all_values[11]	auto[0]	auto[0]	auto[1]	5350351	1			T31	55845		T32	154		T19	12
all_values[11]	auto[0]	auto[1]	auto[0]	590529	1			T31	5667		T32	17		T19	7
all_values[11]	auto[0]	auto[1]	auto[1]	5373362	1			T31	55782		T32	84		T19	11
all_values[11]	auto[1]	auto[0]	auto[1]	78236	1			T31	839		T32	7		T27	2313
all_values[11]	auto[1]	auto[1]	auto[1]	78045	1			T31	811		T32	6		T19	3
all_values[12]	auto[0]	auto[0]	auto[0]	2731481	1			T31	18677		T32	18		T19	23
all_values[12]	auto[0]	auto[0]	auto[1]	5363397	1			T31	55187		T32	131		T19	12
all_values[12]	auto[0]	auto[1]	auto[0]	587468	1			T31	6001		T32	37		T19	6
all_values[12]	auto[0]	auto[1]	auto[1]	5370009	1			T31	55447		T32	148		T19	13
all_values[12]	auto[1]	auto[0]	auto[1]	78501	1			T31	825		T32	8		T19	1
all_values[12]	auto[1]	auto[1]	auto[1]	77538	1			T31	766		T32	9		T19	3
all_values[13]	auto[0]	auto[0]	auto[0]	2744512	1			T31	18396		T32	14		T19	27
all_values[13]	auto[0]	auto[0]	auto[1]	5349403	1			T31	54602		T32	154		T19	3
all_values[13]	auto[0]	auto[1]	auto[0]	581940	1			T31	5497		T32	3		T19	15
all_values[13]	auto[0]	auto[1]	auto[1]	5376549	1			T31	56784		T32	170		T19	9
all_values[13]	auto[1]	auto[0]	auto[1]	77930	1			T31	845		T32	6		T19	1
all_values[13]	auto[1]	auto[1]	auto[1]	78060	1			T31	779		T32	4		T19	3
all_values[14]	auto[0]	auto[0]	auto[0]	2731322	1			T31	17947		T32	28		T19	28
all_values[14]	auto[0]	auto[0]	auto[1]	5408573	1			T31	54791		T32	155		T19	12
all_values[14]	auto[0]	auto[1]	auto[0]	588912	1			T31	5653		T32	6		T19	13
all_values[14]	auto[0]	auto[1]	auto[1]	5323267	1			T31	56868		T32	145		T19	4
all_values[14]	auto[1]	auto[0]	auto[1]	78574	1			T31	853		T32	9		T19	1
all_values[14]	auto[1]	auto[1]	auto[1]	77746	1			T31	791		T32	8		T27	2225
all_values[15]	auto[0]	auto[0]	auto[0]	2731167	1			T31	17717		T32	34		T19	26
all_values[15]	auto[0]	auto[0]	auto[1]	5367890	1			T31	56129		T32	136		T19	3
all_values[15]	auto[0]	auto[1]	auto[0]	596130	1			T31	5853		T32	12		T19	14
all_values[15]	auto[0]	auto[1]	auto[1]	5356801	1			T31	55544		T32	155		T19	11
all_values[15]	auto[1]	auto[0]	auto[1]	78289	1			T31	852		T32	7		T27	2274
all_values[15]	auto[1]	auto[1]	auto[1]	78117	1			T31	808		T32	7		T19	4
all_values[16]	auto[0]	auto[0]	auto[0]	2735978	1			T31	18108		T32	7		T19	35
all_values[16]	auto[0]	auto[0]	auto[1]	5358923	1			T31	57010		T32	198		T19	11
all_values[16]	auto[0]	auto[1]	auto[0]	589406	1			T31	5427		T32	3		T19	5
all_values[16]	auto[0]	auto[1]	auto[1]	5368013	1			T31	54724		T32	131		T19	5
all_values[16]	auto[1]	auto[0]	auto[1]	78161	1			T31	820		T32	8		T19	2
all_values[16]	auto[1]	auto[1]	auto[1]	77913	1			T31	814		T32	4		T27	2312
all_values[17]	auto[0]	auto[0]	auto[0]	2733417	1			T31	17950		T32	29		T19	37
all_values[17]	auto[0]	auto[0]	auto[1]	5379141	1			T31	56078		T32	173		T19	13
all_values[17]	auto[0]	auto[1]	auto[0]	583229	1			T31	5820		T32	26		T19	6
all_values[17]	auto[0]	auto[1]	auto[1]	5356491	1			T31	55445		T32	113		T22	1103
all_values[17]	auto[1]	auto[0]	auto[1]	78281	1			T31	798		T32	5		T19	2
all_values[17]	auto[1]	auto[1]	auto[1]	77835	1			T31	812		T32	5		T27	2269
all_values[18]	auto[0]	auto[0]	auto[0]	2744970	1			T31	19296		T32	43		T19	23
all_values[18]	auto[0]	auto[0]	auto[1]	5371589	1			T31	55610		T32	240		T19	17
all_values[18]	auto[0]	auto[1]	auto[0]	592769	1			T31	6759		T32	17		T19	10
all_values[18]	auto[0]	auto[1]	auto[1]	5342843	1			T31	53562		T32	39		T19	8
all_values[18]	auto[1]	auto[0]	auto[1]	78609	1			T31	828		T32	10		T27	2354
all_values[18]	auto[1]	auto[1]	auto[1]	77614	1			T31	848		T32	2		T27	2296
all_values[19]	auto[0]	auto[0]	auto[0]	2741783	1			T31	17862		T32	18		T19	38
all_values[19]	auto[0]	auto[0]	auto[1]	5380029	1			T31	57922		T32	145		T19	12
all_values[19]	auto[0]	auto[1]	auto[0]	587422	1			T31	5729		T32	32		T19	3
all_values[19]	auto[0]	auto[1]	auto[1]	5343169	1			T31	53749		T32	141		T19	4
all_values[19]	auto[1]	auto[0]	auto[1]	78297	1			T31	856		T32	8		T27	2406
all_values[19]	auto[1]	auto[1]	auto[1]	77694	1			T31	785		T32	7		T19	1
all_values[20]	auto[0]	auto[0]	auto[0]	2729420	1			T31	18169		T32	29		T19	38
all_values[20]	auto[0]	auto[0]	auto[1]	5359177	1			T31	54438		T32	134		T19	7
all_values[20]	auto[0]	auto[1]	auto[0]	583636	1			T31	5491		T32	15		T19	4
all_values[20]	auto[0]	auto[1]	auto[1]	5379885	1			T31	57163		T32	161		T19	7
all_values[20]	auto[1]	auto[0]	auto[1]	78276	1			T31	899		T32	5		T19	2
all_values[20]	auto[1]	auto[1]	auto[1]	78000	1			T31	743		T32	7		T27	2316
all_values[21]	auto[0]	auto[0]	auto[0]	2734640	1			T31	17911		T32	9		T19	34
all_values[21]	auto[0]	auto[0]	auto[1]	5346818	1			T31	55639		T32	200		T19	6
all_values[21]	auto[0]	auto[1]	auto[0]	591916	1			T31	5392		T32	1		T19	6
all_values[21]	auto[0]	auto[1]	auto[1]	5379141	1			T31	56347		T32	127		T19	10
all_values[21]	auto[1]	auto[0]	auto[1]	79006	1			T31	811		T32	9		T27	2411
all_values[21]	auto[1]	auto[1]	auto[1]	76873	1			T31	803		T32	5		T19	2
all_values[22]	auto[0]	auto[0]	auto[0]	2731089	1			T31	18241		T32	7		T19	22
all_values[22]	auto[0]	auto[0]	auto[1]	5385367	1			T31	55185		T32	135		T19	23
all_values[22]	auto[0]	auto[1]	auto[0]	594433	1			T31	5659		T32	28		T22	133
all_values[22]	auto[0]	auto[1]	auto[1]	5341005	1			T31	56192		T32	162		T19	9
all_values[22]	auto[1]	auto[0]	auto[1]	78283	1			T31	790		T32	7		T19	3
all_values[22]	auto[1]	auto[1]	auto[1]	78217	1			T31	836		T32	12		T19	1
all_values[23]	auto[0]	auto[0]	auto[0]	2735292	1			T31	18280		T32	13		T19	27
all_values[23]	auto[0]	auto[0]	auto[1]	5359949	1			T31	56352		T32	134		T19	19
all_values[23]	auto[0]	auto[1]	auto[0]	597635	1			T31	5893		T32	24		T19	4
all_values[23]	auto[0]	auto[1]	auto[1]	5359736	1			T31	54754		T32	163		T19	6
all_values[23]	auto[1]	auto[0]	auto[1]	78289	1			T31	797		T32	10		T19	1
all_values[23]	auto[1]	auto[1]	auto[1]	77493	1			T31	827		T32	7		T19	1
all_values[24]	auto[0]	auto[0]	auto[0]	2738106	1			T31	18572		T32	36		T19	33
all_values[24]	auto[0]	auto[0]	auto[1]	5381067	1			T31	56879		T32	195		T19	6
all_values[24]	auto[0]	auto[1]	auto[0]	589867	1			T31	5817		T32	7		T19	15
all_values[24]	auto[0]	auto[1]	auto[1]	5342962	1			T31	54025		T32	101		T19	1
all_values[24]	auto[1]	auto[0]	auto[1]	77822	1			T31	797		T32	6		T19	3
all_values[24]	auto[1]	auto[1]	auto[1]	78570	1			T31	813		T32	6		T27	2412
all_values[25]	auto[0]	auto[0]	auto[0]	2732911	1			T31	18810		T32	54		T19	25
all_values[25]	auto[0]	auto[0]	auto[1]	5374009	1			T31	53838		T32	128		T19	1
all_values[25]	auto[0]	auto[1]	auto[0]	581366	1			T31	6297		T32	15		T19	12
all_values[25]	auto[0]	auto[1]	auto[1]	5363582	1			T31	56335		T32	138		T19	17
all_values[25]	auto[1]	auto[0]	auto[1]	78835	1			T31	865		T32	3		T27	2328
all_values[25]	auto[1]	auto[1]	auto[1]	77691	1			T31	758		T32	13		T19	3
all_values[26]	auto[0]	auto[0]	auto[0]	2738470	1			T31	17917		T32	6		T19	26
all_values[26]	auto[0]	auto[0]	auto[1]	5392477	1			T31	56489		T32	182		T19	4
all_values[26]	auto[0]	auto[1]	auto[0]	590249	1			T31	6236		T32	16		T19	19
all_values[26]	auto[0]	auto[1]	auto[1]	5330890	1			T31	54659		T32	131		T19	5
all_values[26]	auto[1]	auto[0]	auto[1]	78105	1			T31	783		T32	10		T19	1
all_values[26]	auto[1]	auto[1]	auto[1]	78203	1			T31	819		T32	6		T19	3
all_values[27]	auto[0]	auto[0]	auto[0]	2729410	1			T31	18253		T32	34		T19	30
all_values[27]	auto[0]	auto[0]	auto[1]	5389341	1			T31	57635		T32	186		T19	4
all_values[27]	auto[0]	auto[1]	auto[0]	583822	1			T31	5387		T32	26		T19	5
all_values[27]	auto[0]	auto[1]	auto[1]	5349782	1			T31	53995		T32	92		T19	18
all_values[27]	auto[1]	auto[0]	auto[1]	78074	1			T31	817		T32	10		T27	2342
all_values[27]	auto[1]	auto[1]	auto[1]	77965	1			T31	816		T32	3		T19	1
all_values[28]	auto[0]	auto[0]	auto[0]	2746293	1			T31	18255		T32	4		T19	36
all_values[28]	auto[0]	auto[0]	auto[1]	5333992	1			T31	55347		T32	141		T19	8
all_values[28]	auto[0]	auto[1]	auto[0]	583783	1			T31	6023		T32	23		T19	8
all_values[28]	auto[0]	auto[1]	auto[1]	5387667	1			T31	55626		T32	167		T19	6
all_values[28]	auto[1]	auto[0]	auto[1]	78634	1			T31	855		T32	13		T27	2392
all_values[28]	auto[1]	auto[1]	auto[1]	78025	1			T31	797		T32	3		T27	2324
all_values[29]	auto[0]	auto[0]	auto[0]	2741367	1			T31	17922		T32	16		T19	27
all_values[29]	auto[0]	auto[0]	auto[1]	5346449	1			T31	55954		T32	151		T19	6
all_values[29]	auto[0]	auto[1]	auto[0]	596816	1			T31	6256		T32	13		T19	7
all_values[29]	auto[0]	auto[1]	auto[1]	5367399	1			T31	55117		T32	158		T19	12
all_values[29]	auto[1]	auto[0]	auto[1]	78047	1			T31	842		T32	8		T19	3
all_values[29]	auto[1]	auto[1]	auto[1]	78316	1			T31	812		T32	5		T19	3
all_values[30]	auto[0]	auto[0]	auto[0]	2735148	1			T31	18198		T32	12		T19	30
all_values[30]	auto[0]	auto[0]	auto[1]	5394877	1			T31	56129		T32	125		T19	11
all_values[30]	auto[0]	auto[1]	auto[0]	581391	1			T31	6170		T32	15		T19	8
all_values[30]	auto[0]	auto[1]	auto[1]	5340689	1			T31	54785		T32	181		T19	5
all_values[30]	auto[1]	auto[0]	auto[1]	78260	1			T31	829		T32	8		T19	2
all_values[30]	auto[1]	auto[1]	auto[1]	78029	1			T31	792		T32	10		T19	2
all_values[31]	auto[0]	auto[0]	auto[0]	2736886	1			T31	19261		T32	15		T19	37
all_values[31]	auto[0]	auto[0]	auto[1]	5430732	1			T31	55729		T32	209		T19	4
all_values[31]	auto[0]	auto[1]	auto[0]	584613	1			T31	6376		T32	7		T19	6
all_values[31]	auto[0]	auto[1]	auto[1]	5299826	1			T31	53869		T32	103		T19	8
all_values[31]	auto[1]	auto[0]	auto[1]	78464	1			T31	830		T32	11		T19	1
all_values[31]	auto[1]	auto[1]	auto[1]	77873	1			T31	838		T32	6		T19	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal