Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[1]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[2]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[3]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[4]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[5]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[6]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[7]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[8]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[9]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[10]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[11]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[12]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[13]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[14]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[15]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[16]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[17]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[18]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[19]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[20]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[21]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[22]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[23]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[24]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[25]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[26]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[27]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[28]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[29]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[30]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[31]	13938957	1			T31	132219		T32	347		T19	79

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263544126

1

T31

274180

T32

8506

T19

1416

auto[1]

182502498

1

T31

148920

T32

2598

T19

1112

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

358180687

1

T31

336972

T32

6287

T19

2413

auto[1]

87865937

1

T31

861279

T32

4817

T19

115

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

332241763

1

T31

309228

T32

5636

T19

2167

auto[1]

113804861

1

T31

113872

T32

5468

T19

361

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5143502	1			T31	51866		T32	116		T19	37
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3863562	1			T31	31589		T32	4		T19	23
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1382394	1			T31	14045		T32	117		T19	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1712640	1			T31	20303		T32	50		T19	8
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	471025	1			T31	1486		T32	6		T19	5
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1365834	1			T31	12930		T32	54		T19	4
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5144389	1			T31	52199		T32	109		T19	24
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3867934	1			T31	31571		T32	6		T19	33
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1382762	1			T31	14257		T32	122		T23	56
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1712788	1			T31	19911		T32	32		T19	14
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	468399	1			T31	1544		T19	7		T21	8
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1362685	1			T31	12737		T32	78		T19	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5134109	1			T31	50861		T32	72		T19	21
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3862791	1			T31	31476		T32	3		T19	45
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1380988	1			T31	14088		T32	93		T23	68
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1715743	1			T31	20889		T32	72		T19	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	475334	1			T31	1547		T32	7		T19	3
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1369992	1			T31	13358		T32	100		T19	2
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5131331	1			T31	50781		T32	88		T19	34
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3868801	1			T31	31590		T32	2		T19	17
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1380950	1			T31	13747		T32	46		T19	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1714015	1			T31	20796		T32	135		T19	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	471346	1			T31	1629		T32	3		T19	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1372514	1			T31	13676		T32	73		T19	8
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5136017	1			T31	51767		T32	122		T19	42
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3862049	1			T31	31345		T32	2		T19	32
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1383705	1			T31	13361		T32	45		T21	2
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1713627	1			T31	20809		T32	78		T19	5
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	475096	1			T31	1602		T32	4		T23	27
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1368463	1			T31	13335		T32	96		T23	115
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5141531	1			T31	51721		T32	75		T19	43
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3858205	1			T31	31517		T32	1		T19	29
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1382920	1			T31	13330		T32	67		T19	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1714379	1			T31	20751		T32	127		T19	4
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	472363	1			T31	1579		T32	5		T19	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1369559	1			T31	13321		T32	72		T23	79
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5141558	1			T31	52022		T32	80		T19	37
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3856512	1			T31	31746		T32	3		T19	15
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1384248	1			T31	13654		T32	56		T21	6
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1715301	1			T31	20346		T32	132		T19	9
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	472369	1			T31	1513		T32	3		T19	5
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1368969	1			T31	12938		T32	73		T19	13
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5144061	1			T31	51271		T32	116		T19	37
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3858905	1			T31	31516		T32	2		T19	26
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1382840	1			T31	13774		T32	94		T19	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1716882	1			T31	20552		T32	92		T19	7
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	472742	1			T31	1617		T32	2		T19	6
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1363527	1			T31	13489		T32	41		T19	2
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5143003	1			T31	50867		T32	126		T19	36
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3854436	1			T31	31901		T32	2		T19	33
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1379249	1			T31	13674		T32	84		T23	109
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1717788	1			T31	20918		T32	76		T19	9
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	473476	1			T31	1536		T32	3		T19	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1371005	1			T31	13323		T32	56		T21	4
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5143498	1			T31	51109		T32	80		T19	36
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3859071	1			T31	31797		T32	7		T19	29
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1379666	1			T31	13374		T32	81		T19	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1716074	1			T31	21078		T32	80		T19	10
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	473219	1			T31	1616		T23	41		T24	24
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1367429	1			T31	13245		T32	99		T23	109
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5143600	1			T31	51088		T32	93		T19	46
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3854503	1			T31	31402		T32	3		T19	31
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1375125	1			T31	13557		T32	112		T19	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1719212	1			T31	21002		T32	70		T21	1
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	474284	1			T31	1592		T32	5		T23	34
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1372233	1			T31	13578		T32	64		T23	46
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5142736	1			T31	52090		T32	148		T19	31
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3858058	1			T31	31739		T32	3		T19	38
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1382424	1			T31	13983		T32	44		T23	56
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1712316	1			T31	19665		T32	111		T19	7
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	471958	1			T31	1449		T19	3		T21	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1371465	1			T31	13293		T32	41		T21	2
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5143706	1			T31	51421		T32	121		T19	38
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3855073	1			T31	31668		T32	1		T19	13
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1379246	1			T31	13105		T32	62		T19	4
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1716634	1			T31	20931		T32	89		T19	18
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	472767	1			T31	1534		T32	5		T19	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1371531	1			T31	13560		T32	69		T19	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5134981	1			T31	51125		T32	91		T19	11
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3864988	1			T31	31564		T32	2		T19	46
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1380265	1			T31	13494		T32	68		T21	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1717580	1			T31	20877		T32	138		T19	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	473781	1			T31	1561		T32	1		T19	7
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1367362	1			T31	13598		T32	47		T23	74
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5146420	1			T31	51412		T32	115		T19	23
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3865225	1			T31	31632		T32	4		T19	43
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1382372	1			T31	13380		T32	81		T19	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1709799	1			T31	20861		T32	96		T19	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	469093	1			T31	1426		T32	1		T19	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1366048	1			T31	13508		T32	50		T21	2
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5140587	1			T31	51143		T32	90		T19	44
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3863788	1			T31	31791		T32	5		T19	14
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1381667	1			T31	13550		T32	56		T19	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1714296	1			T31	20519		T32	66		T19	9
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	471468	1			T31	1518		T19	2		T21	6
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1367151	1			T31	13698		T32	130		T19	8
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5138018	1			T31	51200		T32	148		T19	39
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3863387	1			T31	31545		T32	4		T19	34
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1374510	1			T31	13160		T32	89		T19	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1721356	1			T31	21460		T32	66		T19	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	473546	1			T31	1570		T19	2		T21	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1368140	1			T31	13284		T32	40		T19	2
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5144426	1			T31	51429		T32	115		T19	38
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3866468	1			T31	31616		T32	1		T19	23
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1378843	1			T31	13477		T32	55		T19	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1718417	1			T31	20903		T32	128		T19	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	467982	1			T31	1601		T32	3		T19	3
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1362821	1			T31	13193		T32	45		T19	8
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5136037	1			T31	50953		T32	82		T19	44
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3873181	1			T31	31569		T19	28		T22	1059
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1373978	1			T31	13435		T32	29		T19	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1721002	1			T31	21334		T32	136		T21	34
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	472415	1			T31	1512		T32	5		T19	3
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1362344	1			T31	13416		T32	95		T19	2
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5143507	1			T31	52032		T32	108		T19	55
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3859312	1			T31	31629		T32	4		T19	22
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1374867	1			T31	13203		T32	74		T19	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1715660	1			T31	20362		T32	84		T19	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	475403	1			T31	1494		T32	1		T21	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1370208	1			T31	13499		T32	76		T23	59
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5136855	1			T31	51501		T32	37		T19	20
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3870968	1			T31	31752		T32	6		T19	44
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1378933	1			T31	13641		T32	131		T21	4
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1715279	1			T31	20313		T32	56		T19	7
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	471340	1			T31	1479		T32	1		T19	7
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1365582	1			T31	13533		T32	116		T19	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5145607	1			T31	51052		T32	96		T19	58
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3857103	1			T31	31804		T32	6		T19	16
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1374402	1			T31	13372		T32	110		T19	3
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1720695	1			T31	21183		T32	78		T19	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	473831	1			T31	1495		T32	2		T21	12
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1367319	1			T31	13313		T32	55		T21	6
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5137178	1			T31	50949		T32	83		T19	43
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3871986	1			T31	31730		T32	6		T19	33
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1378909	1			T31	13778		T32	61		T19	3
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1712609	1			T31	20791		T32	87		T23	286
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	472808	1			T31	1528		T32	3		T23	35
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1365467	1			T31	13443		T32	107		T23	63
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5142939	1			T31	51160		T32	56		T19	24
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3867459	1			T31	31969		T32	4		T19	38
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1377819	1			T31	14052		T32	69		T19	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1716770	1			T31	20234		T32	114		T19	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	472241	1			T31	1441		T32	2		T19	3
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1361729	1			T31	13363		T32	102		T19	10
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5135704	1			T31	51588		T32	68		T19	43
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3868447	1			T31	31655		T19	26		T21	5
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1375759	1			T31	13265		T32	75		T21	4
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1723076	1			T31	20903		T32	93		T19	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	472540	1			T31	1452		T32	4		T19	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1363431	1			T31	13356		T32	107		T19	4
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5134522	1			T31	51602		T32	123		T19	34
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3872174	1			T31	31663		T32	4		T19	35
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1379107	1			T31	13620		T32	101		T23	51
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1718735	1			T31	20491		T32	66		T19	9
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	471922	1			T31	1569		T32	3		T19	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1362497	1			T31	13274		T32	50		T21	4
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5133169	1			T31	51561		T32	91		T19	25
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3873255	1			T31	31670		T32	1		T19	44
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1376233	1			T31	13609		T32	68		T23	69
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1717571	1			T31	20375		T32	91		T19	10
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	472417	1			T31	1568		T32	4		T21	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1366312	1			T31	13436		T32	92		T21	4
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5140147	1			T31	51293		T32	96		T19	40
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3863282	1			T31	31850		T19	24		T21	6
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1373872	1			T31	13263		T32	99		T19	3
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1720577	1			T31	20561		T32	72		T19	8
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	474327	1			T31	1604		T32	6		T21	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1366752	1			T31	13648		T32	74		T19	4
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5139546	1			T31	51928		T32	80		T19	31
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3863273	1			T31	31698		T19	32		T21	7
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1374621	1			T31	13477		T32	72		T19	1
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1721237	1			T31	20742		T32	111		T19	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	474076	1			T31	1515		T32	9		T19	5
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1366204	1			T31	12859		T32	75		T19	2
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5154175	1			T31	51210		T32	102		T19	44
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3854984	1			T31	31753		T32	2		T19	35
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1373528	1			T31	13461		T32	20		T23	86
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1718499	1			T31	20932		T32	141		T21	31
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	472891	1			T31	1477		T32	2		T21	13
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1364880	1			T31	13386		T32	80		T23	90
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5135935	1			T31	51486		T32	101		T19	46
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3867588	1			T31	31541		T32	2		T19	32
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1377763	1			T31	13603		T32	8		T23	84
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1717011	1			T31	20718		T32	163		T19	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	470307	1			T31	1523		T32	1		T21	6
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1370353	1			T31	13348		T32	72		T21	5
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5137204	1			T31	51601		T32	110		T19	39
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3866221	1			T31	31605		T32	4		T19	28
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1374811	1			T31	13316		T32	115		T19	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1717784	1			T31	20904		T32	34		T19	8
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	475582	1			T31	1557		T19	3		T21	11
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1367355	1			T31	13236		T32	84		T23	76

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal