Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[1]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[2]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[3]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[4]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[5]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[6]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[7]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[8]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[9]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[10]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[11]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[12]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[13]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[14]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[15]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[16]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[17]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[18]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[19]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[20]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[21]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[22]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[23]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[24]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[25]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[26]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[27]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[28]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[29]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[30]	13938957	1			T31	132219		T32	347		T19	79
bins_for_gpio_bits[31]	13938957	1			T31	132219		T32	347		T19	79

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263544126

1

T31

274180

T32

8506

T19

1416

auto[1]

182502498

1

T31

148920

T32

2598

T19

1112

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263537744

1

T31

274155

T32

8506

T19

1414

auto[1]

182508880

1

T31

148945

T32

2598

T19

1114

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7993596	1			T31	83872		T32	275		T19	47
bins_for_gpio_bits[0]	auto[0]	auto[1]	244699	1			T31	2333		T32	8		T21	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	244940	1			T31	2342		T32	8		T21	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	5455722	1			T31	43672		T32	56		T19	32
bins_for_gpio_bits[1]	auto[0]	auto[0]	7995181	1			T31	84097		T32	256		T19	38
bins_for_gpio_bits[1]	auto[0]	auto[1]	244565	1			T31	2259		T32	7		T21	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	244758	1			T31	2270		T32	7		T21	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	5454453	1			T31	43593		T32	77		T19	41
bins_for_gpio_bits[2]	auto[0]	auto[0]	7986539	1			T31	83441		T32	227		T19	29
bins_for_gpio_bits[2]	auto[0]	auto[1]	244107	1			T31	2385		T32	10		T21	2
bins_for_gpio_bits[2]	auto[1]	auto[0]	244301	1			T31	2397		T32	10		T21	2
bins_for_gpio_bits[2]	auto[1]	auto[1]	5464010	1			T31	43996		T32	100		T19	50
bins_for_gpio_bits[3]	auto[0]	auto[0]	7981061	1			T31	82977		T32	260		T19	52
bins_for_gpio_bits[3]	auto[0]	auto[1]	245052	1			T31	2336		T32	9		T23	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	245235	1			T31	2347		T32	9		T19	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	5467609	1			T31	44559		T32	69		T19	26
bins_for_gpio_bits[4]	auto[0]	auto[0]	7988279	1			T31	83649		T32	231		T19	47
bins_for_gpio_bits[4]	auto[0]	auto[1]	244896	1			T31	2280		T32	14		T23	16
bins_for_gpio_bits[4]	auto[1]	auto[0]	245070	1			T31	2288		T32	14		T23	16
bins_for_gpio_bits[4]	auto[1]	auto[1]	5460712	1			T31	44002		T32	88		T19	32
bins_for_gpio_bits[5]	auto[0]	auto[0]	7994009	1			T31	83473		T32	257		T19	49
bins_for_gpio_bits[5]	auto[0]	auto[1]	244616	1			T31	2323		T32	12		T23	15
bins_for_gpio_bits[5]	auto[1]	auto[0]	244821	1			T31	2329		T32	12		T23	15
bins_for_gpio_bits[5]	auto[1]	auto[1]	5455511	1			T31	44094		T32	66		T19	30
bins_for_gpio_bits[6]	auto[0]	auto[0]	7995763	1			T31	83694		T32	257		T19	46
bins_for_gpio_bits[6]	auto[0]	auto[1]	245139	1			T31	2317		T32	11		T23	18
bins_for_gpio_bits[6]	auto[1]	auto[0]	245344	1			T31	2328		T32	11		T23	18
bins_for_gpio_bits[6]	auto[1]	auto[1]	5452711	1			T31	43880		T32	68		T19	33
bins_for_gpio_bits[7]	auto[0]	auto[0]	7998223	1			T31	83256		T32	294		T19	45
bins_for_gpio_bits[7]	auto[0]	auto[1]	245317	1			T31	2334		T32	8		T23	15
bins_for_gpio_bits[7]	auto[1]	auto[0]	245560	1			T31	2341		T32	8		T23	15
bins_for_gpio_bits[7]	auto[1]	auto[1]	5449857	1			T31	44288		T32	37		T19	34
bins_for_gpio_bits[8]	auto[0]	auto[0]	7994772	1			T31	83115		T32	279		T19	45
bins_for_gpio_bits[8]	auto[0]	auto[1]	245082	1			T31	2334		T32	7		T21	1
bins_for_gpio_bits[8]	auto[1]	auto[0]	245268	1			T31	2344		T32	7		T21	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	5453835	1			T31	44426		T32	54		T19	34
bins_for_gpio_bits[9]	auto[0]	auto[0]	7995381	1			T31	83267		T32	229		T19	50
bins_for_gpio_bits[9]	auto[0]	auto[1]	243686	1			T31	2285		T32	12		T23	18
bins_for_gpio_bits[9]	auto[1]	auto[0]	243857	1			T31	2294		T32	12		T23	18
bins_for_gpio_bits[9]	auto[1]	auto[1]	5456033	1			T31	44373		T32	94		T19	29
bins_for_gpio_bits[10]	auto[0]	auto[0]	7992520	1			T31	83295		T32	264		T19	48
bins_for_gpio_bits[10]	auto[0]	auto[1]	245245	1			T31	2341		T32	11		T23	10
bins_for_gpio_bits[10]	auto[1]	auto[0]	245417	1			T31	2352		T32	11		T23	10
bins_for_gpio_bits[10]	auto[1]	auto[1]	5455775	1			T31	44231		T32	61		T19	31
bins_for_gpio_bits[11]	auto[0]	auto[0]	7992796	1			T31	83407		T32	295		T19	38
bins_for_gpio_bits[11]	auto[0]	auto[1]	244434	1			T31	2321		T32	8		T21	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	244680	1			T31	2331		T32	8		T21	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	5457047	1			T31	44160		T32	36		T19	41
bins_for_gpio_bits[12]	auto[0]	auto[0]	7994682	1			T31	83146		T32	263		T19	60
bins_for_gpio_bits[12]	auto[0]	auto[1]	244693	1			T31	2305		T32	9		T23	11
bins_for_gpio_bits[12]	auto[1]	auto[0]	244904	1			T31	2311		T32	9		T23	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	5454678	1			T31	44457		T32	66		T19	19
bins_for_gpio_bits[13]	auto[0]	auto[0]	7988036	1			T31	83155		T32	289		T19	26
bins_for_gpio_bits[13]	auto[0]	auto[1]	244555	1			T31	2334		T32	8		T23	16
bins_for_gpio_bits[13]	auto[1]	auto[0]	244790	1			T31	2341		T32	8		T23	16
bins_for_gpio_bits[13]	auto[1]	auto[1]	5461576	1			T31	44389		T32	42		T19	53
bins_for_gpio_bits[14]	auto[0]	auto[0]	7993522	1			T31	83265		T32	283		T19	31
bins_for_gpio_bits[14]	auto[0]	auto[1]	244883	1			T31	2374		T32	9		T21	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	245069	1			T31	2388		T32	9		T21	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	5455483	1			T31	44192		T32	46		T19	48
bins_for_gpio_bits[15]	auto[0]	auto[0]	7991885	1			T31	82889		T32	202		T19	55
bins_for_gpio_bits[15]	auto[0]	auto[1]	244437	1			T31	2314		T32	10		T19	1
bins_for_gpio_bits[15]	auto[1]	auto[0]	244665	1			T31	2323		T32	10		T23	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	5457970	1			T31	44693		T32	125		T19	23
bins_for_gpio_bits[16]	auto[0]	auto[0]	7989037	1			T31	83539		T32	295		T19	41
bins_for_gpio_bits[16]	auto[0]	auto[1]	244667	1			T31	2274		T32	8		T21	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	244847	1			T31	2281		T32	8		T21	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	5460406	1			T31	44125		T32	36		T19	38
bins_for_gpio_bits[17]	auto[0]	auto[0]	7996790	1			T31	83450		T32	289		T19	44
bins_for_gpio_bits[17]	auto[0]	auto[1]	244719	1			T31	2352		T32	9		T21	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	244896	1			T31	2359		T32	9		T19	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	5452552	1			T31	44058		T32	40		T19	34
bins_for_gpio_bits[18]	auto[0]	auto[0]	7986242	1			T31	83359		T32	238		T19	46
bins_for_gpio_bits[18]	auto[0]	auto[1]	244564	1			T31	2352		T32	9		T21	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	244775	1			T31	2363		T32	9		T21	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	5463376	1			T31	44145		T32	91		T19	33
bins_for_gpio_bits[19]	auto[0]	auto[0]	7988634	1			T31	83233		T32	253		T19	57
bins_for_gpio_bits[19]	auto[0]	auto[1]	245207	1			T31	2362		T32	13		T23	10
bins_for_gpio_bits[19]	auto[1]	auto[0]	245400	1			T31	2364		T32	13		T23	10
bins_for_gpio_bits[19]	auto[1]	auto[1]	5459716	1			T31	44260		T32	68		T19	22
bins_for_gpio_bits[20]	auto[0]	auto[0]	7985688	1			T31	83093		T32	208		T19	27
bins_for_gpio_bits[20]	auto[0]	auto[1]	245205	1			T31	2358		T32	16		T23	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	245379	1			T31	2362		T32	16		T23	17
bins_for_gpio_bits[20]	auto[1]	auto[1]	5462685	1			T31	44406		T32	107		T19	52
bins_for_gpio_bits[21]	auto[0]	auto[0]	7995101	1			T31	83223		T32	273		T19	63
bins_for_gpio_bits[21]	auto[0]	auto[1]	245418	1			T31	2379		T32	11		T21	3
bins_for_gpio_bits[21]	auto[1]	auto[0]	245603	1			T31	2384		T32	11		T21	3
bins_for_gpio_bits[21]	auto[1]	auto[1]	5452835	1			T31	44233		T32	52		T19	16
bins_for_gpio_bits[22]	auto[0]	auto[0]	7984044	1			T31	83151		T32	217		T19	46
bins_for_gpio_bits[22]	auto[0]	auto[1]	244425	1			T31	2358		T32	14		T23	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	244652	1			T31	2367		T32	14		T23	12
bins_for_gpio_bits[22]	auto[1]	auto[1]	5465836	1			T31	44343		T32	102		T19	33
bins_for_gpio_bits[23]	auto[0]	auto[0]	7993133	1			T31	83071		T32	225		T19	27
bins_for_gpio_bits[23]	auto[0]	auto[1]	244179	1			T31	2367		T32	14		T23	13
bins_for_gpio_bits[23]	auto[1]	auto[0]	244395	1			T31	2375		T32	14		T19	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	5457250	1			T31	44406		T32	94		T19	51
bins_for_gpio_bits[24]	auto[0]	auto[0]	7989136	1			T31	83411		T32	226		T19	47
bins_for_gpio_bits[24]	auto[0]	auto[1]	245191	1			T31	2337		T32	10		T19	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	245403	1			T31	2345		T32	10		T19	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	5459227	1			T31	44126		T32	101		T19	30
bins_for_gpio_bits[25]	auto[0]	auto[0]	7987347	1			T31	83340		T32	281		T19	43
bins_for_gpio_bits[25]	auto[0]	auto[1]	244821	1			T31	2369		T32	9		T21	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	245017	1			T31	2373		T32	9		T21	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	5461772	1			T31	44137		T32	48		T19	36
bins_for_gpio_bits[26]	auto[0]	auto[0]	7981915	1			T31	83190		T32	236		T19	35
bins_for_gpio_bits[26]	auto[0]	auto[1]	244864	1			T31	2347		T32	14		T21	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	245058	1			T31	2355		T32	14		T21	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	5467120	1			T31	44327		T32	83		T19	44
bins_for_gpio_bits[27]	auto[0]	auto[0]	7989863	1			T31	82784		T32	258		T19	50
bins_for_gpio_bits[27]	auto[0]	auto[1]	244603	1			T31	2326		T32	9		T19	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	244733	1			T31	2333		T32	9		T19	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	5459758	1			T31	44776		T32	71		T19	27
bins_for_gpio_bits[28]	auto[0]	auto[0]	7990316	1			T31	83858		T32	250		T19	40
bins_for_gpio_bits[28]	auto[0]	auto[1]	244902	1			T31	2283		T32	13		T23	18
bins_for_gpio_bits[28]	auto[1]	auto[0]	245088	1			T31	2289		T32	13		T23	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	5458651	1			T31	43789		T32	71		T19	39
bins_for_gpio_bits[29]	auto[0]	auto[0]	8001078	1			T31	83245		T32	247		T19	44
bins_for_gpio_bits[29]	auto[0]	auto[1]	244916	1			T31	2351		T32	16		T23	18
bins_for_gpio_bits[29]	auto[1]	auto[0]	245124	1			T31	2358		T32	16		T23	18
bins_for_gpio_bits[29]	auto[1]	auto[1]	5447839	1			T31	44265		T32	68		T19	35
bins_for_gpio_bits[30]	auto[0]	auto[0]	7985393	1			T31	83440		T32	265		T19	47
bins_for_gpio_bits[30]	auto[0]	auto[1]	245134	1			T31	2363		T32	7		T21	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	245316	1			T31	2367		T32	7		T21	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	5463114	1			T31	44049		T32	68		T19	32
bins_for_gpio_bits[31]	auto[0]	auto[0]	7984747	1			T31	83485		T32	249		T19	48
bins_for_gpio_bits[31]	auto[0]	auto[1]	244814	1			T31	2330		T32	10		T23	13
bins_for_gpio_bits[31]	auto[1]	auto[0]	245052	1			T31	2336		T32	10		T23	13
bins_for_gpio_bits[31]	auto[1]	auto[1]	5464344	1			T31	44068		T32	78		T19	31