Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8204072 |
1 |
|
|
T31 |
76741 |
|
T32 |
216 |
|
T19 |
40 |
| auto[1] |
6004322 |
1 |
|
|
T31 |
60162 |
|
T32 |
135 |
|
T19 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13434702 |
1 |
|
|
T31 |
128693 |
|
T32 |
341 |
|
T19 |
58 |
| auto[1] |
773692 |
1 |
|
|
T31 |
8210 |
|
T32 |
10 |
|
T22 |
192 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166122 |
1 |
|
|
T31 |
75533 |
|
T32 |
77 |
|
T19 |
55 |
| auto[1] |
6042272 |
1 |
|
|
T31 |
61370 |
|
T32 |
274 |
|
T19 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2631522 |
1 |
|
|
T31 |
27928 |
|
T32 |
184 |
|
T22 |
510 |
| auto[1] |
auto[0] |
auto[1] |
385945 |
1 |
|
|
T31 |
4368 |
|
T32 |
7 |
|
T22 |
123 |
| auto[1] |
auto[1] |
auto[0] |
2637058 |
1 |
|
|
T31 |
25232 |
|
T32 |
80 |
|
T19 |
3 |
| auto[1] |
auto[1] |
auto[1] |
387747 |
1 |
|
|
T31 |
3842 |
|
T32 |
3 |
|
T22 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8178738 |
1 |
|
|
T31 |
72690 |
|
T32 |
169 |
|
T19 |
46 |
| auto[1] |
6029656 |
1 |
|
|
T31 |
64213 |
|
T32 |
182 |
|
T19 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13436060 |
1 |
|
|
T31 |
128693 |
|
T32 |
345 |
|
T19 |
58 |
| auto[1] |
772334 |
1 |
|
|
T31 |
8210 |
|
T32 |
6 |
|
T22 |
265 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8182873 |
1 |
|
|
T31 |
75854 |
|
T32 |
147 |
|
T19 |
51 |
| auto[1] |
6025521 |
1 |
|
|
T31 |
61049 |
|
T32 |
204 |
|
T19 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2625427 |
1 |
|
|
T31 |
25335 |
|
T32 |
86 |
|
T19 |
7 |
| auto[1] |
auto[0] |
auto[1] |
386533 |
1 |
|
|
T31 |
3920 |
|
T32 |
2 |
|
T22 |
145 |
| auto[1] |
auto[1] |
auto[0] |
2627760 |
1 |
|
|
T31 |
27504 |
|
T32 |
112 |
|
T22 |
487 |
| auto[1] |
auto[1] |
auto[1] |
385801 |
1 |
|
|
T31 |
4290 |
|
T32 |
4 |
|
T22 |
120 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8171575 |
1 |
|
|
T31 |
73375 |
|
T32 |
164 |
|
T19 |
28 |
| auto[1] |
6036819 |
1 |
|
|
T31 |
63528 |
|
T32 |
187 |
|
T19 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13440422 |
1 |
|
|
T31 |
128657 |
|
T32 |
348 |
|
T19 |
58 |
| auto[1] |
767972 |
1 |
|
|
T31 |
8246 |
|
T32 |
3 |
|
T22 |
351 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8209729 |
1 |
|
|
T31 |
74560 |
|
T32 |
174 |
|
T19 |
38 |
| auto[1] |
5998665 |
1 |
|
|
T31 |
62343 |
|
T32 |
177 |
|
T19 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2615530 |
1 |
|
|
T31 |
27461 |
|
T32 |
73 |
|
T19 |
2 |
| auto[1] |
auto[0] |
auto[1] |
384111 |
1 |
|
|
T31 |
4180 |
|
T32 |
2 |
|
T22 |
203 |
| auto[1] |
auto[1] |
auto[0] |
2615163 |
1 |
|
|
T31 |
26636 |
|
T32 |
101 |
|
T19 |
18 |
| auto[1] |
auto[1] |
auto[1] |
383861 |
1 |
|
|
T31 |
4066 |
|
T32 |
1 |
|
T22 |
148 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166458 |
1 |
|
|
T31 |
74643 |
|
T32 |
244 |
|
T19 |
37 |
| auto[1] |
6041936 |
1 |
|
|
T31 |
62260 |
|
T32 |
107 |
|
T19 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13433986 |
1 |
|
|
T31 |
128745 |
|
T32 |
344 |
|
T19 |
57 |
| auto[1] |
774408 |
1 |
|
|
T31 |
8158 |
|
T32 |
7 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8156941 |
1 |
|
|
T31 |
74145 |
|
T32 |
154 |
|
T19 |
52 |
| auto[1] |
6051453 |
1 |
|
|
T31 |
62758 |
|
T32 |
197 |
|
T19 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2630819 |
1 |
|
|
T31 |
27584 |
|
T32 |
146 |
|
T19 |
5 |
| auto[1] |
auto[0] |
auto[1] |
385915 |
1 |
|
|
T31 |
4118 |
|
T32 |
4 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2646226 |
1 |
|
|
T31 |
27016 |
|
T32 |
44 |
|
T22 |
796 |
| auto[1] |
auto[1] |
auto[1] |
388493 |
1 |
|
|
T31 |
4040 |
|
T32 |
3 |
|
T22 |
204 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8173379 |
1 |
|
|
T31 |
74689 |
|
T32 |
157 |
|
T19 |
36 |
| auto[1] |
6035015 |
1 |
|
|
T31 |
62214 |
|
T32 |
194 |
|
T19 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13442388 |
1 |
|
|
T31 |
128561 |
|
T32 |
343 |
|
T19 |
58 |
| auto[1] |
766006 |
1 |
|
|
T31 |
8342 |
|
T32 |
8 |
|
T22 |
322 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8216544 |
1 |
|
|
T31 |
73588 |
|
T32 |
86 |
|
T19 |
54 |
| auto[1] |
5991850 |
1 |
|
|
T31 |
63315 |
|
T32 |
265 |
|
T19 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2605879 |
1 |
|
|
T31 |
27324 |
|
T32 |
120 |
|
T22 |
418 |
| auto[1] |
auto[0] |
auto[1] |
382065 |
1 |
|
|
T31 |
4076 |
|
T32 |
4 |
|
T22 |
109 |
| auto[1] |
auto[1] |
auto[0] |
2619965 |
1 |
|
|
T31 |
27649 |
|
T32 |
137 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
383941 |
1 |
|
|
T31 |
4266 |
|
T32 |
4 |
|
T22 |
213 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8171845 |
1 |
|
|
T31 |
73843 |
|
T32 |
174 |
|
T19 |
31 |
| auto[1] |
6036549 |
1 |
|
|
T31 |
63060 |
|
T32 |
177 |
|
T19 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13438087 |
1 |
|
|
T31 |
128494 |
|
T32 |
346 |
|
T19 |
58 |
| auto[1] |
770307 |
1 |
|
|
T31 |
8409 |
|
T32 |
5 |
|
T22 |
259 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8185638 |
1 |
|
|
T31 |
72754 |
|
T32 |
92 |
|
T19 |
45 |
| auto[1] |
6022756 |
1 |
|
|
T31 |
64149 |
|
T32 |
259 |
|
T19 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2615794 |
1 |
|
|
T31 |
27761 |
|
T32 |
117 |
|
T19 |
9 |
| auto[1] |
auto[0] |
auto[1] |
383111 |
1 |
|
|
T31 |
4191 |
|
T32 |
4 |
|
T22 |
120 |
| auto[1] |
auto[1] |
auto[0] |
2636655 |
1 |
|
|
T31 |
27979 |
|
T32 |
137 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
387196 |
1 |
|
|
T31 |
4218 |
|
T32 |
1 |
|
T22 |
139 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218469 |
1 |
|
|
T31 |
73591 |
|
T32 |
192 |
|
T19 |
41 |
| auto[1] |
5989925 |
1 |
|
|
T31 |
63312 |
|
T32 |
159 |
|
T19 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13434145 |
1 |
|
|
T31 |
128397 |
|
T32 |
341 |
|
T19 |
57 |
| auto[1] |
774249 |
1 |
|
|
T31 |
8506 |
|
T32 |
10 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8170321 |
1 |
|
|
T31 |
73073 |
|
T32 |
146 |
|
T19 |
45 |
| auto[1] |
6038073 |
1 |
|
|
T31 |
63830 |
|
T32 |
205 |
|
T19 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2653340 |
1 |
|
|
T31 |
26636 |
|
T32 |
109 |
|
T19 |
12 |
| auto[1] |
auto[0] |
auto[1] |
391622 |
1 |
|
|
T31 |
4065 |
|
T32 |
4 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2610484 |
1 |
|
|
T31 |
28688 |
|
T32 |
86 |
|
T22 |
453 |
| auto[1] |
auto[1] |
auto[1] |
382627 |
1 |
|
|
T31 |
4441 |
|
T32 |
6 |
|
T22 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8177346 |
1 |
|
|
T31 |
74698 |
|
T32 |
177 |
|
T19 |
29 |
| auto[1] |
6031048 |
1 |
|
|
T31 |
62205 |
|
T32 |
174 |
|
T19 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13433017 |
1 |
|
|
T31 |
128193 |
|
T32 |
344 |
|
T19 |
58 |
| auto[1] |
775377 |
1 |
|
|
T31 |
8710 |
|
T32 |
7 |
|
T22 |
259 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8161341 |
1 |
|
|
T31 |
72578 |
|
T32 |
128 |
|
T19 |
55 |
| auto[1] |
6047053 |
1 |
|
|
T31 |
64325 |
|
T32 |
223 |
|
T19 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2635321 |
1 |
|
|
T31 |
27624 |
|
T32 |
124 |
|
T22 |
525 |
| auto[1] |
auto[0] |
auto[1] |
387739 |
1 |
|
|
T31 |
4276 |
|
T32 |
4 |
|
T22 |
131 |
| auto[1] |
auto[1] |
auto[0] |
2636355 |
1 |
|
|
T31 |
27991 |
|
T32 |
92 |
|
T19 |
3 |
| auto[1] |
auto[1] |
auto[1] |
387638 |
1 |
|
|
T31 |
4434 |
|
T32 |
3 |
|
T22 |
128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8173062 |
1 |
|
|
T31 |
75938 |
|
T32 |
213 |
|
T19 |
48 |
| auto[1] |
6035332 |
1 |
|
|
T31 |
60965 |
|
T32 |
138 |
|
T19 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13440366 |
1 |
|
|
T31 |
128789 |
|
T32 |
347 |
|
T19 |
58 |
| auto[1] |
768028 |
1 |
|
|
T31 |
8114 |
|
T32 |
4 |
|
T22 |
272 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8206911 |
1 |
|
|
T31 |
75179 |
|
T32 |
159 |
|
T19 |
45 |
| auto[1] |
6001483 |
1 |
|
|
T31 |
61724 |
|
T32 |
192 |
|
T19 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2610883 |
1 |
|
|
T31 |
26933 |
|
T32 |
124 |
|
T19 |
9 |
| auto[1] |
auto[0] |
auto[1] |
383047 |
1 |
|
|
T31 |
4048 |
|
T32 |
2 |
|
T22 |
144 |
| auto[1] |
auto[1] |
auto[0] |
2622572 |
1 |
|
|
T31 |
26677 |
|
T32 |
64 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
384981 |
1 |
|
|
T31 |
4066 |
|
T32 |
2 |
|
T22 |
128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8190839 |
1 |
|
|
T31 |
74826 |
|
T32 |
207 |
|
T19 |
52 |
| auto[1] |
6017555 |
1 |
|
|
T31 |
62077 |
|
T32 |
144 |
|
T19 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13438775 |
1 |
|
|
T31 |
128482 |
|
T32 |
346 |
|
T19 |
58 |
| auto[1] |
769619 |
1 |
|
|
T31 |
8421 |
|
T32 |
5 |
|
T22 |
212 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8192605 |
1 |
|
|
T31 |
74749 |
|
T32 |
177 |
|
T19 |
54 |
| auto[1] |
6015789 |
1 |
|
|
T31 |
62154 |
|
T32 |
174 |
|
T19 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2619847 |
1 |
|
|
T31 |
27451 |
|
T32 |
96 |
|
T19 |
4 |
| auto[1] |
auto[0] |
auto[1] |
384131 |
1 |
|
|
T31 |
4362 |
|
T32 |
3 |
|
T22 |
122 |
| auto[1] |
auto[1] |
auto[0] |
2626323 |
1 |
|
|
T31 |
26282 |
|
T32 |
73 |
|
T22 |
376 |
| auto[1] |
auto[1] |
auto[1] |
385488 |
1 |
|
|
T31 |
4059 |
|
T32 |
2 |
|
T22 |
90 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8195168 |
1 |
|
|
T31 |
75734 |
|
T32 |
293 |
|
T19 |
40 |
| auto[1] |
6013226 |
1 |
|
|
T31 |
61169 |
|
T32 |
58 |
|
T19 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13440170 |
1 |
|
|
T31 |
128733 |
|
T32 |
349 |
|
T19 |
58 |
| auto[1] |
768224 |
1 |
|
|
T31 |
8170 |
|
T32 |
2 |
|
T22 |
265 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8208484 |
1 |
|
|
T31 |
75730 |
|
T32 |
205 |
|
T19 |
41 |
| auto[1] |
5999910 |
1 |
|
|
T31 |
61173 |
|
T32 |
146 |
|
T19 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2627188 |
1 |
|
|
T31 |
26955 |
|
T32 |
122 |
|
T19 |
13 |
| auto[1] |
auto[0] |
auto[1] |
386452 |
1 |
|
|
T31 |
4153 |
|
T32 |
1 |
|
T22 |
125 |
| auto[1] |
auto[1] |
auto[0] |
2604498 |
1 |
|
|
T31 |
26048 |
|
T32 |
22 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
381772 |
1 |
|
|
T31 |
4017 |
|
T32 |
1 |
|
T22 |
140 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8200109 |
1 |
|
|
T31 |
76640 |
|
T32 |
171 |
|
T19 |
50 |
| auto[1] |
6008285 |
1 |
|
|
T31 |
60263 |
|
T32 |
180 |
|
T19 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13442099 |
1 |
|
|
T31 |
128524 |
|
T32 |
344 |
|
T19 |
56 |
| auto[1] |
766295 |
1 |
|
|
T31 |
8379 |
|
T32 |
7 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8215976 |
1 |
|
|
T31 |
74734 |
|
T32 |
160 |
|
T19 |
35 |
| auto[1] |
5992418 |
1 |
|
|
T31 |
62169 |
|
T32 |
191 |
|
T19 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2614175 |
1 |
|
|
T31 |
27984 |
|
T32 |
77 |
|
T19 |
14 |
| auto[1] |
auto[0] |
auto[1] |
382003 |
1 |
|
|
T31 |
4286 |
|
T32 |
1 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2611948 |
1 |
|
|
T31 |
25806 |
|
T32 |
107 |
|
T19 |
7 |
| auto[1] |
auto[1] |
auto[1] |
384292 |
1 |
|
|
T31 |
4093 |
|
T32 |
6 |
|
T22 |
115 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8207844 |
1 |
|
|
T31 |
74143 |
|
T32 |
105 |
|
T19 |
34 |
| auto[1] |
6000550 |
1 |
|
|
T31 |
62760 |
|
T32 |
246 |
|
T19 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13435067 |
1 |
|
|
T31 |
128648 |
|
T32 |
345 |
|
T19 |
58 |
| auto[1] |
773327 |
1 |
|
|
T31 |
8255 |
|
T32 |
6 |
|
T22 |
241 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8163464 |
1 |
|
|
T31 |
75131 |
|
T32 |
205 |
|
T19 |
38 |
| auto[1] |
6044930 |
1 |
|
|
T31 |
61772 |
|
T32 |
146 |
|
T19 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2649311 |
1 |
|
|
T31 |
27033 |
|
T32 |
66 |
|
T19 |
7 |
| auto[1] |
auto[0] |
auto[1] |
389358 |
1 |
|
|
T31 |
4263 |
|
T32 |
5 |
|
T22 |
121 |
| auto[1] |
auto[1] |
auto[0] |
2622292 |
1 |
|
|
T31 |
26484 |
|
T32 |
74 |
|
T19 |
13 |
| auto[1] |
auto[1] |
auto[1] |
383969 |
1 |
|
|
T31 |
3992 |
|
T32 |
1 |
|
T22 |
120 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166873 |
1 |
|
|
T31 |
73506 |
|
T32 |
168 |
|
T19 |
47 |
| auto[1] |
6041521 |
1 |
|
|
T31 |
63397 |
|
T32 |
183 |
|
T19 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13435698 |
1 |
|
|
T31 |
128854 |
|
T32 |
338 |
|
T19 |
58 |
| auto[1] |
772696 |
1 |
|
|
T31 |
8049 |
|
T32 |
13 |
|
T22 |
256 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8178576 |
1 |
|
|
T31 |
76499 |
|
T32 |
93 |
|
T19 |
48 |
| auto[1] |
6029818 |
1 |
|
|
T31 |
60404 |
|
T32 |
258 |
|
T19 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2624926 |
1 |
|
|
T31 |
26488 |
|
T32 |
114 |
|
T19 |
10 |
| auto[1] |
auto[0] |
auto[1] |
385685 |
1 |
|
|
T31 |
4004 |
|
T32 |
5 |
|
T22 |
131 |
| auto[1] |
auto[1] |
auto[0] |
2632196 |
1 |
|
|
T31 |
25867 |
|
T32 |
131 |
|
T22 |
507 |
| auto[1] |
auto[1] |
auto[1] |
387011 |
1 |
|
|
T31 |
4045 |
|
T32 |
8 |
|
T22 |
125 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8160464 |
1 |
|
|
T31 |
74361 |
|
T32 |
218 |
|
T19 |
40 |
| auto[1] |
6047930 |
1 |
|
|
T31 |
62542 |
|
T32 |
133 |
|
T19 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13430538 |
1 |
|
|
T31 |
128825 |
|
T32 |
346 |
|
T19 |
58 |
| auto[1] |
777856 |
1 |
|
|
T31 |
8078 |
|
T32 |
5 |
|
T22 |
226 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8146093 |
1 |
|
|
T31 |
76548 |
|
T32 |
194 |
|
T19 |
52 |
| auto[1] |
6062301 |
1 |
|
|
T31 |
60355 |
|
T32 |
157 |
|
T19 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2630373 |
1 |
|
|
T31 |
27253 |
|
T32 |
104 |
|
T19 |
6 |
| auto[1] |
auto[0] |
auto[1] |
385063 |
1 |
|
|
T31 |
4127 |
|
T32 |
4 |
|
T22 |
124 |
| auto[1] |
auto[1] |
auto[0] |
2654072 |
1 |
|
|
T31 |
25024 |
|
T32 |
48 |
|
T22 |
433 |
| auto[1] |
auto[1] |
auto[1] |
392793 |
1 |
|
|
T31 |
3951 |
|
T32 |
1 |
|
T22 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8194739 |
1 |
|
|
T31 |
74216 |
|
T32 |
149 |
|
T19 |
48 |
| auto[1] |
6013655 |
1 |
|
|
T31 |
62687 |
|
T32 |
202 |
|
T19 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13434401 |
1 |
|
|
T31 |
128705 |
|
T32 |
341 |
|
T19 |
57 |
| auto[1] |
773993 |
1 |
|
|
T31 |
8198 |
|
T32 |
10 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8164732 |
1 |
|
|
T31 |
75672 |
|
T32 |
166 |
|
T19 |
36 |
| auto[1] |
6043662 |
1 |
|
|
T31 |
61231 |
|
T32 |
185 |
|
T19 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2635745 |
1 |
|
|
T31 |
26647 |
|
T32 |
50 |
|
T19 |
17 |
| auto[1] |
auto[0] |
auto[1] |
386563 |
1 |
|
|
T31 |
4143 |
|
T32 |
4 |
|
T22 |
162 |
| auto[1] |
auto[1] |
auto[0] |
2633924 |
1 |
|
|
T31 |
26386 |
|
T32 |
125 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
387430 |
1 |
|
|
T31 |
4055 |
|
T32 |
6 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8173530 |
1 |
|
|
T31 |
75429 |
|
T32 |
157 |
|
T19 |
47 |
| auto[1] |
6034864 |
1 |
|
|
T31 |
61474 |
|
T32 |
194 |
|
T19 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13435872 |
1 |
|
|
T31 |
128407 |
|
T32 |
339 |
|
T19 |
58 |
| auto[1] |
772522 |
1 |
|
|
T31 |
8496 |
|
T32 |
12 |
|
T22 |
285 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8173306 |
1 |
|
|
T31 |
73461 |
|
T32 |
173 |
|
T19 |
41 |
| auto[1] |
6035088 |
1 |
|
|
T31 |
63442 |
|
T32 |
178 |
|
T19 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2620564 |
1 |
|
|
T31 |
28273 |
|
T32 |
100 |
|
T19 |
8 |
| auto[1] |
auto[0] |
auto[1] |
385019 |
1 |
|
|
T31 |
4383 |
|
T32 |
7 |
|
T22 |
132 |
| auto[1] |
auto[1] |
auto[0] |
2642002 |
1 |
|
|
T31 |
26673 |
|
T32 |
66 |
|
T19 |
9 |
| auto[1] |
auto[1] |
auto[1] |
387503 |
1 |
|
|
T31 |
4113 |
|
T32 |
5 |
|
T22 |
153 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8196995 |
1 |
|
|
T31 |
76248 |
|
T32 |
237 |
|
T19 |
42 |
| auto[1] |
6011399 |
1 |
|
|
T31 |
60655 |
|
T32 |
114 |
|
T19 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13437110 |
1 |
|
|
T31 |
128669 |
|
T32 |
345 |
|
T19 |
58 |
| auto[1] |
771284 |
1 |
|
|
T31 |
8234 |
|
T32 |
6 |
|
T22 |
371 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8187173 |
1 |
|
|
T31 |
75704 |
|
T32 |
160 |
|
T19 |
54 |
| auto[1] |
6021221 |
1 |
|
|
T31 |
61199 |
|
T32 |
191 |
|
T19 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2632148 |
1 |
|
|
T31 |
27212 |
|
T32 |
126 |
|
T22 |
816 |
| auto[1] |
auto[0] |
auto[1] |
387931 |
1 |
|
|
T31 |
4190 |
|
T32 |
3 |
|
T22 |
203 |
| auto[1] |
auto[1] |
auto[0] |
2617789 |
1 |
|
|
T31 |
25753 |
|
T32 |
59 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
383353 |
1 |
|
|
T31 |
4044 |
|
T32 |
3 |
|
T22 |
168 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8185755 |
1 |
|
|
T31 |
73513 |
|
T32 |
185 |
|
T19 |
26 |
| auto[1] |
6022639 |
1 |
|
|
T31 |
63390 |
|
T32 |
166 |
|
T19 |
32 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13439436 |
1 |
|
|
T31 |
129041 |
|
T32 |
346 |
|
T19 |
56 |
| auto[1] |
768958 |
1 |
|
|
T31 |
7862 |
|
T32 |
5 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8210185 |
1 |
|
|
T31 |
76821 |
|
T32 |
210 |
|
T19 |
35 |
| auto[1] |
5998209 |
1 |
|
|
T31 |
60082 |
|
T32 |
141 |
|
T19 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2624033 |
1 |
|
|
T31 |
26472 |
|
T32 |
38 |
|
T19 |
3 |
| auto[1] |
auto[0] |
auto[1] |
385345 |
1 |
|
|
T31 |
3985 |
|
T19 |
1 |
|
T22 |
122 |
| auto[1] |
auto[1] |
auto[0] |
2605218 |
1 |
|
|
T31 |
25748 |
|
T32 |
98 |
|
T19 |
18 |
| auto[1] |
auto[1] |
auto[1] |
383613 |
1 |
|
|
T31 |
3877 |
|
T32 |
5 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8209052 |
1 |
|
|
T31 |
75189 |
|
T32 |
198 |
|
T19 |
31 |
| auto[1] |
5999342 |
1 |
|
|
T31 |
61714 |
|
T32 |
153 |
|
T19 |
27 |