Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8154181 |
1 |
|
|
T31 |
74716 |
|
T32 |
219 |
|
T19 |
53 |
| auto[1] |
6054213 |
1 |
|
|
T31 |
62187 |
|
T32 |
132 |
|
T19 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13437423 |
1 |
|
|
T31 |
128445 |
|
T32 |
348 |
|
T19 |
58 |
| auto[1] |
770971 |
1 |
|
|
T31 |
8458 |
|
T32 |
3 |
|
T22 |
246 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8187833 |
1 |
|
|
T31 |
74166 |
|
T32 |
250 |
|
T19 |
48 |
| auto[1] |
6020561 |
1 |
|
|
T31 |
62737 |
|
T32 |
101 |
|
T19 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2613570 |
1 |
|
|
T31 |
26853 |
|
T32 |
49 |
|
T19 |
10 |
| auto[1] |
auto[0] |
auto[1] |
381854 |
1 |
|
|
T31 |
4086 |
|
T22 |
146 |
|
T27 |
11704 |
| auto[1] |
auto[1] |
auto[0] |
2636020 |
1 |
|
|
T31 |
27426 |
|
T32 |
49 |
|
T22 |
386 |
| auto[1] |
auto[1] |
auto[1] |
389117 |
1 |
|
|
T31 |
4372 |
|
T32 |
3 |
|
T22 |
100 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |