Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8188411 |
1 |
|
|
T31 |
72042 |
|
T32 |
74 |
|
T19 |
42 |
| auto[1] |
6019983 |
1 |
|
|
T31 |
64861 |
|
T32 |
277 |
|
T19 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13438492 |
1 |
|
|
T31 |
128429 |
|
T32 |
345 |
|
T19 |
57 |
| auto[1] |
769902 |
1 |
|
|
T31 |
8474 |
|
T32 |
6 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8191963 |
1 |
|
|
T31 |
73991 |
|
T32 |
142 |
|
T19 |
32 |
| auto[1] |
6016431 |
1 |
|
|
T31 |
62912 |
|
T32 |
209 |
|
T19 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2653460 |
1 |
|
|
T31 |
26140 |
|
T32 |
45 |
|
T19 |
12 |
| auto[1] |
auto[0] |
auto[1] |
390489 |
1 |
|
|
T31 |
3974 |
|
T32 |
2 |
|
T22 |
74 |
| auto[1] |
auto[1] |
auto[0] |
2593069 |
1 |
|
|
T31 |
28298 |
|
T32 |
158 |
|
T19 |
13 |
| auto[1] |
auto[1] |
auto[1] |
379413 |
1 |
|
|
T31 |
4500 |
|
T32 |
4 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |