Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8202789 |
1 |
|
|
T31 |
74890 |
|
T32 |
97 |
|
T19 |
41 |
| auto[1] |
6005605 |
1 |
|
|
T31 |
62013 |
|
T32 |
254 |
|
T19 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13436295 |
1 |
|
|
T31 |
128213 |
|
T32 |
347 |
|
T19 |
57 |
| auto[1] |
772099 |
1 |
|
|
T31 |
8690 |
|
T32 |
4 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8175867 |
1 |
|
|
T31 |
72054 |
|
T32 |
185 |
|
T19 |
35 |
| auto[1] |
6032527 |
1 |
|
|
T31 |
64849 |
|
T32 |
166 |
|
T19 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2632543 |
1 |
|
|
T31 |
28818 |
|
T32 |
45 |
|
T19 |
9 |
| auto[1] |
auto[0] |
auto[1] |
385600 |
1 |
|
|
T31 |
4512 |
|
T19 |
1 |
|
T22 |
111 |
| auto[1] |
auto[1] |
auto[0] |
2627885 |
1 |
|
|
T31 |
27341 |
|
T32 |
117 |
|
T19 |
13 |
| auto[1] |
auto[1] |
auto[1] |
386499 |
1 |
|
|
T31 |
4178 |
|
T32 |
4 |
|
T22 |
169 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |