Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8190814 |
1 |
|
|
T31 |
74645 |
|
T32 |
124 |
|
T19 |
50 |
| auto[1] |
6017580 |
1 |
|
|
T31 |
62258 |
|
T32 |
227 |
|
T19 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13439016 |
1 |
|
|
T31 |
128205 |
|
T32 |
344 |
|
T19 |
58 |
| auto[1] |
769378 |
1 |
|
|
T31 |
8698 |
|
T32 |
7 |
|
T22 |
326 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8190211 |
1 |
|
|
T31 |
71131 |
|
T32 |
168 |
|
T19 |
32 |
| auto[1] |
6018183 |
1 |
|
|
T31 |
65772 |
|
T32 |
183 |
|
T19 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2640295 |
1 |
|
|
T31 |
29688 |
|
T32 |
75 |
|
T19 |
18 |
| auto[1] |
auto[0] |
auto[1] |
386819 |
1 |
|
|
T31 |
4559 |
|
T32 |
2 |
|
T22 |
116 |
| auto[1] |
auto[1] |
auto[0] |
2608510 |
1 |
|
|
T31 |
27386 |
|
T32 |
101 |
|
T19 |
8 |
| auto[1] |
auto[1] |
auto[1] |
382559 |
1 |
|
|
T31 |
4139 |
|
T32 |
5 |
|
T22 |
210 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |