Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8182862 |
1 |
|
|
T31 |
72832 |
|
T32 |
179 |
|
T19 |
48 |
| auto[1] |
6025532 |
1 |
|
|
T31 |
64071 |
|
T32 |
172 |
|
T19 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13435712 |
1 |
|
|
T31 |
128478 |
|
T32 |
340 |
|
T19 |
58 |
| auto[1] |
772682 |
1 |
|
|
T31 |
8425 |
|
T32 |
11 |
|
T22 |
291 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8178641 |
1 |
|
|
T31 |
73236 |
|
T32 |
143 |
|
T19 |
52 |
| auto[1] |
6029753 |
1 |
|
|
T31 |
63667 |
|
T32 |
208 |
|
T19 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2616409 |
1 |
|
|
T31 |
26859 |
|
T32 |
98 |
|
T19 |
6 |
| auto[1] |
auto[0] |
auto[1] |
383400 |
1 |
|
|
T31 |
4023 |
|
T32 |
6 |
|
T22 |
133 |
| auto[1] |
auto[1] |
auto[0] |
2640662 |
1 |
|
|
T31 |
28383 |
|
T32 |
99 |
|
T22 |
673 |
| auto[1] |
auto[1] |
auto[1] |
389282 |
1 |
|
|
T31 |
4402 |
|
T32 |
5 |
|
T22 |
158 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |