Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8204072 |
1 |
|
|
T31 |
76741 |
|
T32 |
216 |
|
T19 |
40 |
| auto[1] |
6004322 |
1 |
|
|
T31 |
60162 |
|
T32 |
135 |
|
T19 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11703109 |
1 |
|
|
T31 |
111963 |
|
T32 |
334 |
|
T19 |
58 |
| auto[1] |
2505285 |
1 |
|
|
T31 |
24940 |
|
T32 |
17 |
|
T22 |
778 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8186798 |
1 |
|
|
T31 |
73364 |
|
T32 |
158 |
|
T19 |
56 |
| auto[1] |
6021596 |
1 |
|
|
T31 |
63539 |
|
T32 |
193 |
|
T19 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1768263 |
1 |
|
|
T31 |
19639 |
|
T32 |
113 |
|
T22 |
468 |
| auto[1] |
auto[0] |
auto[1] |
1262014 |
1 |
|
|
T31 |
12795 |
|
T32 |
6 |
|
T22 |
517 |
| auto[1] |
auto[1] |
auto[0] |
1748048 |
1 |
|
|
T31 |
18960 |
|
T32 |
63 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1243271 |
1 |
|
|
T31 |
12145 |
|
T32 |
11 |
|
T22 |
261 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |