Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8171575 |
1 |
|
|
T31 |
73375 |
|
T32 |
164 |
|
T19 |
28 |
| auto[1] |
6036819 |
1 |
|
|
T31 |
63528 |
|
T32 |
187 |
|
T19 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11707969 |
1 |
|
|
T31 |
112845 |
|
T32 |
313 |
|
T19 |
56 |
| auto[1] |
2500425 |
1 |
|
|
T31 |
24058 |
|
T32 |
38 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8210181 |
1 |
|
|
T31 |
75817 |
|
T32 |
211 |
|
T19 |
52 |
| auto[1] |
5998213 |
1 |
|
|
T31 |
61086 |
|
T32 |
140 |
|
T19 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1752582 |
1 |
|
|
T31 |
18601 |
|
T32 |
58 |
|
T22 |
346 |
| auto[1] |
auto[0] |
auto[1] |
1252209 |
1 |
|
|
T31 |
12052 |
|
T32 |
18 |
|
T22 |
383 |
| auto[1] |
auto[1] |
auto[0] |
1745206 |
1 |
|
|
T31 |
18427 |
|
T32 |
44 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1248216 |
1 |
|
|
T31 |
12006 |
|
T32 |
20 |
|
T19 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |