Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166458 |
1 |
|
|
T31 |
74643 |
|
T32 |
244 |
|
T19 |
37 |
| auto[1] |
6041936 |
1 |
|
|
T31 |
62260 |
|
T32 |
107 |
|
T19 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11705559 |
1 |
|
|
T31 |
112267 |
|
T32 |
348 |
|
T19 |
58 |
| auto[1] |
2502835 |
1 |
|
|
T31 |
24636 |
|
T32 |
3 |
|
T22 |
699 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8189920 |
1 |
|
|
T31 |
74656 |
|
T32 |
243 |
|
T19 |
56 |
| auto[1] |
6018474 |
1 |
|
|
T31 |
62247 |
|
T32 |
108 |
|
T19 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1742475 |
1 |
|
|
T31 |
18464 |
|
T32 |
75 |
|
T19 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1240211 |
1 |
|
|
T31 |
12037 |
|
T32 |
2 |
|
T22 |
262 |
| auto[1] |
auto[1] |
auto[0] |
1773164 |
1 |
|
|
T31 |
19147 |
|
T32 |
30 |
|
T22 |
439 |
| auto[1] |
auto[1] |
auto[1] |
1262624 |
1 |
|
|
T31 |
12599 |
|
T32 |
1 |
|
T22 |
437 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |