Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8173379 |
1 |
|
|
T31 |
74689 |
|
T32 |
157 |
|
T19 |
36 |
auto[1] |
6035015 |
1 |
|
|
T31 |
62214 |
|
T32 |
194 |
|
T19 |
22 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11692435 |
1 |
|
|
T31 |
112283 |
|
T32 |
311 |
|
T19 |
58 |
auto[1] |
2515959 |
1 |
|
|
T31 |
24620 |
|
T32 |
40 |
|
T22 |
740 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8158341 |
1 |
|
|
T31 |
75147 |
|
T32 |
154 |
|
T19 |
56 |
auto[1] |
6050053 |
1 |
|
|
T31 |
61756 |
|
T32 |
197 |
|
T19 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1766884 |
1 |
|
|
T31 |
19388 |
|
T32 |
45 |
|
T19 |
2 |
auto[1] |
auto[0] |
auto[1] |
1255225 |
1 |
|
|
T31 |
12733 |
|
T32 |
7 |
|
T22 |
304 |
auto[1] |
auto[1] |
auto[0] |
1767210 |
1 |
|
|
T31 |
17748 |
|
T32 |
112 |
|
T22 |
422 |
auto[1] |
auto[1] |
auto[1] |
1260734 |
1 |
|
|
T31 |
11887 |
|
T32 |
33 |
|
T22 |
436 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |