Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13437757 |
1 |
|
|
T31 |
127972 |
|
T32 |
340 |
|
T19 |
57 |
| auto[1] |
770637 |
1 |
|
|
T31 |
8931 |
|
T32 |
11 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8187913 |
1 |
|
|
T31 |
71470 |
|
T32 |
118 |
|
T19 |
39 |
| auto[1] |
6020481 |
1 |
|
|
T31 |
65433 |
|
T32 |
233 |
|
T19 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2639876 |
1 |
|
|
T31 |
28352 |
|
T32 |
120 |
|
T19 |
9 |
| auto[1] |
auto[0] |
auto[1] |
388545 |
1 |
|
|
T31 |
4529 |
|
T32 |
3 |
|
T22 |
172 |
| auto[1] |
auto[1] |
auto[0] |
2609968 |
1 |
|
|
T31 |
28150 |
|
T32 |
102 |
|
T19 |
9 |
| auto[1] |
auto[1] |
auto[1] |
382092 |
1 |
|
|
T31 |
4402 |
|
T32 |
8 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |