Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218469 |
1 |
|
|
T31 |
73591 |
|
T32 |
192 |
|
T19 |
41 |
| auto[1] |
5989925 |
1 |
|
|
T31 |
63312 |
|
T32 |
159 |
|
T19 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11711235 |
1 |
|
|
T31 |
113094 |
|
T32 |
311 |
|
T19 |
56 |
| auto[1] |
2497159 |
1 |
|
|
T31 |
23809 |
|
T32 |
40 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218622 |
1 |
|
|
T31 |
76371 |
|
T32 |
142 |
|
T19 |
54 |
| auto[1] |
5989772 |
1 |
|
|
T31 |
60532 |
|
T32 |
209 |
|
T19 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1766290 |
1 |
|
|
T31 |
18313 |
|
T32 |
102 |
|
T19 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1262262 |
1 |
|
|
T31 |
11621 |
|
T32 |
19 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1726323 |
1 |
|
|
T31 |
18410 |
|
T32 |
67 |
|
T22 |
340 |
| auto[1] |
auto[1] |
auto[1] |
1234897 |
1 |
|
|
T31 |
12188 |
|
T32 |
21 |
|
T22 |
378 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |