Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8177346 |
1 |
|
|
T31 |
74698 |
|
T32 |
177 |
|
T19 |
29 |
| auto[1] |
6031048 |
1 |
|
|
T31 |
62205 |
|
T32 |
174 |
|
T19 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11692240 |
1 |
|
|
T31 |
111787 |
|
T32 |
318 |
|
T19 |
56 |
| auto[1] |
2516154 |
1 |
|
|
T31 |
25116 |
|
T32 |
33 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166410 |
1 |
|
|
T31 |
71860 |
|
T32 |
268 |
|
T19 |
54 |
| auto[1] |
6041984 |
1 |
|
|
T31 |
65043 |
|
T32 |
83 |
|
T19 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1762598 |
1 |
|
|
T31 |
20104 |
|
T32 |
6 |
|
T22 |
387 |
| auto[1] |
auto[0] |
auto[1] |
1260004 |
1 |
|
|
T31 |
12299 |
|
T32 |
23 |
|
T22 |
413 |
| auto[1] |
auto[1] |
auto[0] |
1763232 |
1 |
|
|
T31 |
19823 |
|
T32 |
44 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1256150 |
1 |
|
|
T31 |
12817 |
|
T32 |
10 |
|
T19 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |