Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8207844 |
1 |
|
|
T31 |
74143 |
|
T32 |
105 |
|
T19 |
34 |
| auto[1] |
6000550 |
1 |
|
|
T31 |
62760 |
|
T32 |
246 |
|
T19 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11708254 |
1 |
|
|
T31 |
111869 |
|
T32 |
291 |
|
T19 |
56 |
| auto[1] |
2500140 |
1 |
|
|
T31 |
25034 |
|
T32 |
60 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8208708 |
1 |
|
|
T31 |
73160 |
|
T32 |
138 |
|
T19 |
56 |
| auto[1] |
5999686 |
1 |
|
|
T31 |
63743 |
|
T32 |
213 |
|
T19 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1751982 |
1 |
|
|
T31 |
19397 |
|
T32 |
45 |
|
T22 |
387 |
| auto[1] |
auto[0] |
auto[1] |
1249765 |
1 |
|
|
T31 |
12757 |
|
T32 |
5 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1747564 |
1 |
|
|
T31 |
19312 |
|
T32 |
108 |
|
T22 |
268 |
| auto[1] |
auto[1] |
auto[1] |
1250375 |
1 |
|
|
T31 |
12277 |
|
T32 |
55 |
|
T22 |
218 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |