Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166873 |
1 |
|
|
T31 |
73506 |
|
T32 |
168 |
|
T19 |
47 |
| auto[1] |
6041521 |
1 |
|
|
T31 |
63397 |
|
T32 |
183 |
|
T19 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11703722 |
1 |
|
|
T31 |
112619 |
|
T32 |
323 |
|
T19 |
56 |
| auto[1] |
2504672 |
1 |
|
|
T31 |
24284 |
|
T32 |
28 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8196397 |
1 |
|
|
T31 |
75737 |
|
T32 |
244 |
|
T19 |
56 |
| auto[1] |
6011997 |
1 |
|
|
T31 |
61166 |
|
T32 |
107 |
|
T19 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1749428 |
1 |
|
|
T31 |
17914 |
|
T32 |
42 |
|
T22 |
440 |
| auto[1] |
auto[0] |
auto[1] |
1252213 |
1 |
|
|
T31 |
11712 |
|
T32 |
5 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1757897 |
1 |
|
|
T31 |
18968 |
|
T32 |
37 |
|
T22 |
306 |
| auto[1] |
auto[1] |
auto[1] |
1252459 |
1 |
|
|
T31 |
12572 |
|
T32 |
23 |
|
T22 |
282 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |