Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8160464 |
1 |
|
|
T31 |
74361 |
|
T32 |
218 |
|
T19 |
40 |
| auto[1] |
6047930 |
1 |
|
|
T31 |
62542 |
|
T32 |
133 |
|
T19 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11693942 |
1 |
|
|
T31 |
111765 |
|
T32 |
333 |
|
T19 |
58 |
| auto[1] |
2514452 |
1 |
|
|
T31 |
25138 |
|
T32 |
18 |
|
T22 |
771 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8169852 |
1 |
|
|
T31 |
72482 |
|
T32 |
190 |
|
T19 |
54 |
| auto[1] |
6038542 |
1 |
|
|
T31 |
64421 |
|
T32 |
161 |
|
T19 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1763379 |
1 |
|
|
T31 |
20572 |
|
T32 |
77 |
|
T19 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1254296 |
1 |
|
|
T31 |
12708 |
|
T32 |
9 |
|
T22 |
340 |
| auto[1] |
auto[1] |
auto[0] |
1760711 |
1 |
|
|
T31 |
18711 |
|
T32 |
66 |
|
T22 |
391 |
| auto[1] |
auto[1] |
auto[1] |
1260156 |
1 |
|
|
T31 |
12430 |
|
T32 |
9 |
|
T22 |
431 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |