Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8196825 |
1 |
|
|
T31 |
76705 |
|
T32 |
230 |
|
T19 |
34 |
| auto[1] |
6011569 |
1 |
|
|
T31 |
60198 |
|
T32 |
121 |
|
T19 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13433574 |
1 |
|
|
T31 |
128196 |
|
T32 |
344 |
|
T19 |
57 |
| auto[1] |
774820 |
1 |
|
|
T31 |
8707 |
|
T32 |
7 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8164744 |
1 |
|
|
T31 |
72546 |
|
T32 |
123 |
|
T19 |
35 |
| auto[1] |
6043650 |
1 |
|
|
T31 |
64357 |
|
T32 |
228 |
|
T19 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2647180 |
1 |
|
|
T31 |
29004 |
|
T32 |
152 |
|
T19 |
10 |
| auto[1] |
auto[0] |
auto[1] |
390011 |
1 |
|
|
T31 |
4633 |
|
T32 |
6 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2621650 |
1 |
|
|
T31 |
26646 |
|
T32 |
69 |
|
T19 |
12 |
| auto[1] |
auto[1] |
auto[1] |
384809 |
1 |
|
|
T31 |
4074 |
|
T32 |
1 |
|
T22 |
139 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |