Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8194739 |
1 |
|
|
T31 |
74216 |
|
T32 |
149 |
|
T19 |
48 |
| auto[1] |
6013655 |
1 |
|
|
T31 |
62687 |
|
T32 |
202 |
|
T19 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11700405 |
1 |
|
|
T31 |
112720 |
|
T32 |
296 |
|
T19 |
58 |
| auto[1] |
2507989 |
1 |
|
|
T31 |
24183 |
|
T32 |
55 |
|
T22 |
615 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8179977 |
1 |
|
|
T31 |
75934 |
|
T32 |
222 |
|
T19 |
54 |
| auto[1] |
6028417 |
1 |
|
|
T31 |
60969 |
|
T32 |
129 |
|
T19 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1763300 |
1 |
|
|
T31 |
17584 |
|
T32 |
33 |
|
T19 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1261825 |
1 |
|
|
T31 |
11876 |
|
T32 |
27 |
|
T22 |
358 |
| auto[1] |
auto[1] |
auto[0] |
1757128 |
1 |
|
|
T31 |
19202 |
|
T32 |
41 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1246164 |
1 |
|
|
T31 |
12307 |
|
T32 |
28 |
|
T22 |
257 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |