Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8196995 |
1 |
|
|
T31 |
76248 |
|
T32 |
237 |
|
T19 |
42 |
| auto[1] |
6011399 |
1 |
|
|
T31 |
60655 |
|
T32 |
114 |
|
T19 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11713047 |
1 |
|
|
T31 |
112720 |
|
T32 |
291 |
|
T19 |
58 |
| auto[1] |
2495347 |
1 |
|
|
T31 |
24183 |
|
T32 |
60 |
|
T22 |
839 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8210078 |
1 |
|
|
T31 |
75228 |
|
T32 |
210 |
|
T19 |
58 |
| auto[1] |
5998316 |
1 |
|
|
T31 |
61675 |
|
T32 |
141 |
|
T22 |
1641 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1755202 |
1 |
|
|
T31 |
18607 |
|
T32 |
61 |
|
T22 |
402 |
| auto[1] |
auto[0] |
auto[1] |
1250812 |
1 |
|
|
T31 |
12312 |
|
T32 |
42 |
|
T22 |
410 |
| auto[1] |
auto[1] |
auto[0] |
1747767 |
1 |
|
|
T31 |
18885 |
|
T32 |
20 |
|
T22 |
400 |
| auto[1] |
auto[1] |
auto[1] |
1244535 |
1 |
|
|
T31 |
11871 |
|
T32 |
18 |
|
T22 |
429 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |