Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8158919 |
1 |
|
|
T31 |
74457 |
|
T32 |
158 |
|
T19 |
44 |
| auto[1] |
6049475 |
1 |
|
|
T31 |
62446 |
|
T32 |
193 |
|
T19 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13435746 |
1 |
|
|
T31 |
128670 |
|
T32 |
341 |
|
T19 |
58 |
| auto[1] |
772648 |
1 |
|
|
T31 |
8233 |
|
T32 |
10 |
|
T22 |
238 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8184009 |
1 |
|
|
T31 |
75614 |
|
T32 |
142 |
|
T19 |
58 |
| auto[1] |
6024385 |
1 |
|
|
T31 |
61289 |
|
T32 |
209 |
|
T22 |
1218 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2623128 |
1 |
|
|
T31 |
26997 |
|
T32 |
99 |
|
T22 |
371 |
| auto[1] |
auto[0] |
auto[1] |
384565 |
1 |
|
|
T31 |
4105 |
|
T32 |
4 |
|
T22 |
93 |
| auto[1] |
auto[1] |
auto[0] |
2628609 |
1 |
|
|
T31 |
26059 |
|
T32 |
100 |
|
T22 |
609 |
| auto[1] |
auto[1] |
auto[1] |
388083 |
1 |
|
|
T31 |
4128 |
|
T32 |
6 |
|
T22 |
145 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |