Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8165863 |
1 |
|
|
T31 |
74718 |
|
T32 |
175 |
|
T19 |
36 |
| auto[1] |
6042531 |
1 |
|
|
T31 |
62185 |
|
T32 |
176 |
|
T19 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13432730 |
1 |
|
|
T31 |
128651 |
|
T32 |
341 |
|
T19 |
57 |
| auto[1] |
775664 |
1 |
|
|
T31 |
8252 |
|
T32 |
10 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8168361 |
1 |
|
|
T31 |
75253 |
|
T32 |
170 |
|
T19 |
32 |
| auto[1] |
6040033 |
1 |
|
|
T31 |
61650 |
|
T32 |
181 |
|
T19 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2625200 |
1 |
|
|
T31 |
26875 |
|
T32 |
55 |
|
T19 |
6 |
| auto[1] |
auto[0] |
auto[1] |
387021 |
1 |
|
|
T31 |
4203 |
|
T32 |
3 |
|
T22 |
146 |
| auto[1] |
auto[1] |
auto[0] |
2639169 |
1 |
|
|
T31 |
26523 |
|
T32 |
116 |
|
T19 |
19 |
| auto[1] |
auto[1] |
auto[1] |
388643 |
1 |
|
|
T31 |
4049 |
|
T32 |
7 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |