Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8168755 |
1 |
|
|
T31 |
72706 |
|
T32 |
189 |
|
T19 |
50 |
| auto[1] |
6039639 |
1 |
|
|
T31 |
64197 |
|
T32 |
162 |
|
T19 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13435466 |
1 |
|
|
T31 |
128539 |
|
T32 |
346 |
|
T19 |
58 |
| auto[1] |
772928 |
1 |
|
|
T31 |
8364 |
|
T32 |
5 |
|
T22 |
249 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8181862 |
1 |
|
|
T31 |
74117 |
|
T32 |
172 |
|
T19 |
35 |
| auto[1] |
6026532 |
1 |
|
|
T31 |
62786 |
|
T32 |
179 |
|
T19 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2608882 |
1 |
|
|
T31 |
26241 |
|
T32 |
97 |
|
T19 |
16 |
| auto[1] |
auto[0] |
auto[1] |
383569 |
1 |
|
|
T31 |
3979 |
|
T32 |
4 |
|
T22 |
132 |
| auto[1] |
auto[1] |
auto[0] |
2644722 |
1 |
|
|
T31 |
28181 |
|
T32 |
77 |
|
T19 |
7 |
| auto[1] |
auto[1] |
auto[1] |
389359 |
1 |
|
|
T31 |
4385 |
|
T32 |
1 |
|
T22 |
117 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |