Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8208285 |
1 |
|
|
T31 |
75156 |
|
T32 |
145 |
|
T19 |
43 |
| auto[1] |
6000109 |
1 |
|
|
T31 |
61747 |
|
T32 |
206 |
|
T19 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13434852 |
1 |
|
|
T31 |
128589 |
|
T32 |
346 |
|
T19 |
58 |
| auto[1] |
773542 |
1 |
|
|
T31 |
8314 |
|
T32 |
5 |
|
T22 |
231 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8164646 |
1 |
|
|
T31 |
73956 |
|
T32 |
130 |
|
T19 |
58 |
| auto[1] |
6043748 |
1 |
|
|
T31 |
62947 |
|
T32 |
221 |
|
T22 |
1255 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2654491 |
1 |
|
|
T31 |
27429 |
|
T32 |
79 |
|
T22 |
514 |
| auto[1] |
auto[0] |
auto[1] |
390280 |
1 |
|
|
T31 |
4071 |
|
T32 |
1 |
|
T22 |
118 |
| auto[1] |
auto[1] |
auto[0] |
2615715 |
1 |
|
|
T31 |
27204 |
|
T32 |
137 |
|
T22 |
510 |
| auto[1] |
auto[1] |
auto[1] |
383262 |
1 |
|
|
T31 |
4243 |
|
T32 |
4 |
|
T22 |
113 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |